Re: [RFC PATCH 0/2] MIPS: Loongson: ExtCC clocksource support

From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: kernel@xen0n.name
Cc: linux-mips@linux-mips.org, Paul Burton <paul.burton@mips.com>,
	linux-mips@vger.kernel.org, James Hogan <jhogan@kernel.org>,
	Ralf Baechle <ralf@linux-mips.org>,
	Wang Xuerui <wangxuerui@qiniu.com>,
	Huacai Chen <chenhc@lemote.com>
Subject: Re: [RFC PATCH 0/2] MIPS: Loongson: ExtCC clocksource support
Date: Mon, 25 Feb 2019 13:28:29 +0800	[thread overview]
Message-ID: <20190225082840.SZReoeJx@smtp4o.mail.yandex.net> (raw)

2019年2月24日 下午5:36于 kernel@xen0n.name写道：
>
> From: Wang Xuerui <wangxuerui@qiniu.com> 
>
> Hi, 
>
> This is my WIP patchset to add support for using the on-chip ExtCC 
> (external counter) register as clocksource, to boost the real-time 
> performance on Loongson platform. I'm posting this to solicit comments 
> and get some of the unresolved questions answered. 

Hi Xuerui

Thanks a lot for your works, however, the ExtCC can be influenced by the frequency of CPU core, and we have cpufreq working on Loongson-3 processors, so you should mark it conflict with cpufreq driver.

And as far as I know, ExtCC is even not synchronous between different cores.

I'd prefer to use gs3_HPT(0x3ff00408)  register to implement this feather. Also it can be accessed from all the nodes, and the clock comes from "node clock" which will not effected by core frequency.
>
> * I don't have access to multi-socket ccNUMA Loongson boards. The code 
>   most certainly doesn't work on such hardware, so either someone with 
>   expertise would teach me how to do this, or get this done on their 
>   own. 
> * I'm not sure of the pipeline behavior of the rdhwr instruction used. 
>   The current implementation has a sync (roughly the x86 way), and I'm 
>   not sure if it can be safely omitted, or even moved into the delay 
>   slot on return. 
> * Clock skew can be a concern, but it seems there's no generic mechanism 
>   for clocksource calibration. The x86 code has one supporting PIT/HPET- 
>   based calibration, but that code never got extracted to common 
>   framework. 
> * The VDSO performance seems very bad comparing to x86, even after 
>   adjusting for the cycle frequency difference. But I haven't thoroughly 
>   profiled this and perhaps won't have enough spare time for doing so 
>   (kernel work isn't part of my day job).  So maybe someone could 
>   provide some hints in this area? 
>
> Can only come up with so many points for now; I'll add if more ideas 
> turn up. 
>
> P.S. I have to change to my personal address for outgoing mails; my 
> work address is hosted on QQ Enterprise Mail, which most certainly is 
> blocked altogether by linux-mips.org. 
>
> Wang Xuerui (2): 
>   MIPS: Loongson: add extcc clocksource 
>   MIPS: VDSO: support extcc-based timekeeping 
>
> arch/mips/include/asm/clocksource.h           |  1 + 
> arch/mips/include/asm/mach-loongson64/extcc.h | 26 +++++++++ 
> arch/mips/loongson64/Kconfig                  | 13 +++++ 
> arch/mips/loongson64/common/Makefile          |  5 ++ 
> arch/mips/loongson64/common/extcc.c           | 54 +++++++++++++++++++ 
> arch/mips/loongson64/common/time.c            |  7 +++ 
> arch/mips/vdso/gettimeofday.c                 |  8 +++ 
> 7 files changed, 114 insertions(+) 
> create mode 100644 arch/mips/include/asm/mach-loongson64/extcc.h 
> create mode 100644 arch/mips/loongson64/common/extcc.c 
>
> -- 
> 2.20.1 
>