[PATCH 0/4] MIPS: Exception vector improvements

[PATCH 0/4] MIPS: Exception vector improvements

[Paul Burton]

This series improves the way we allocate memory for our exception vector
& configure it in EBase.

Patch 2 in particular is important preparation for changes being made by
Serge Semin in his "mips: Post-bootmem-memblock transition fixes"
series.

Paul Burton (4):
  MIPS: Use mnemblock_phys_alloc() for exception vector
  MIPS: Always allocate exception vector for MIPSr2+
  MIPS: Sync icache for whole exception vector
  MIPS: Remove duplicate EBase configuration

 arch/mips/kernel/traps.c | 63 ++++++++++++++--------------------------
 1 file changed, 22 insertions(+), 41 deletions(-)

-- 
2.21.0

[PATCH 1/4] MIPS: Use memblock_phys_alloc() for exception vector

[Paul Burton]

Allocate the exception vector using memblock_phys_alloc() which gives us
a physical address, rather than the previous convoluted setup which
obtained a virtual address using memblock_alloc(), converted it to a
physical address & then back to a virtual address.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---
 arch/mips/kernel/traps.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 98ca55d62201..00f44b16385e 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2292,9 +2292,8 @@ void __init trap_init(void)
 		unsigned long size = 0x200 + VECTORSPACING*64;
 		phys_addr_t ebase_pa;
 
-		ebase = (unsigned long)
-			memblock_alloc(size, 1 << fls(size));
-		if (!ebase)
+		ebase_pa = memblock_phys_alloc(size, 1 << fls(size));
+		if (!ebase_pa)
 			panic("%s: Failed to allocate %lu bytes align=0x%x\n",
 			      __func__, size, 1 << fls(size));
 
@@ -2309,9 +2308,10 @@ void __init trap_init(void)
 		 * EVA is special though as it allows segments to be rearranged
 		 * and to become uncached during cache error handling.
 		 */
-		ebase_pa = __pa(ebase);
 		if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
 			ebase = CKSEG0ADDR(ebase_pa);
+		else
+			ebase = (unsigned long)phys_to_virt(ebase_pa);
 	} else {
 		ebase = CAC_BASE;
 
-- 
2.21.0

[PATCH 2/4] MIPS: Always allocate exception vector for MIPSr2+

[Paul Burton]

Currently we allocate the exception vector on systems which use a
vectored interrupt mode, but otherwise attempt to reuse whatever
exception vector the bootloader uses.

This can be problematic for a number of reasons:

  1) The memory isn't properly marked reserved in the memblock
     allocator. We've relied on the fact that EBase is generally in the
     memory below the kernel image which we don't free, but this is
     about to change.

  2) Recent versions of U-Boot place their exception vector high in
     kseg0, in memory which isn't protected by being lower than the
     kernel anyway & can end up being clobbered.

  3) We are unnecessarily reliant upon there being memory at the address
     EBase points to upon entry to the kernel. This is often the case,
     but if the bootloader doesn't configure EBase & leaves it with its
     default value then we rely upon there being memory at physical
     address 0 for no good reason.

Improve this situation by allocating the exception vector in all cases
when running on MIPSr2 or higher, and reserving the memory for MIPSr1 or
lower. This ensures we don't clobber the exception vector in any
configuration, and for MIPSr2 & higher removes the need for memory at
physical address 0.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---
 arch/mips/kernel/traps.c | 35 +++++++++++++++--------------------
 1 file changed, 15 insertions(+), 20 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 00f44b16385e..9b565ed51662 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2284,18 +2284,27 @@ void __init trap_init(void)
 	extern char except_vec3_generic;
 	extern char except_vec4;
 	extern char except_vec3_r4000;
-	unsigned long i;
+	unsigned long i, vec_size;
+	phys_addr_t ebase_pa;
 
 	check_wait();
 
-	if (cpu_has_veic || cpu_has_vint) {
-		unsigned long size = 0x200 + VECTORSPACING*64;
-		phys_addr_t ebase_pa;
+	if (!cpu_has_mips_r2_r6) {
+		ebase = CAC_BASE;
+		ebase_pa = virt_to_phys((void *)ebase);
+		vec_size = 0x400;
+
+		memblock_reserve(ebase_pa, vec_size);
+	} else {
+		if (cpu_has_veic || cpu_has_vint)
+			vec_size = 0x200 + VECTORSPACING*64;
+		else
+			vec_size = PAGE_SIZE;
 
-		ebase_pa = memblock_phys_alloc(size, 1 << fls(size));
+		ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
 		if (!ebase_pa)
 			panic("%s: Failed to allocate %lu bytes align=0x%x\n",
-			      __func__, size, 1 << fls(size));
+			      __func__, vec_size, 1 << fls(vec_size));
 
 		/*
 		 * Try to ensure ebase resides in KSeg0 if possible.
@@ -2312,20 +2321,6 @@ void __init trap_init(void)
 			ebase = CKSEG0ADDR(ebase_pa);
 		else
 			ebase = (unsigned long)phys_to_virt(ebase_pa);
-	} else {
-		ebase = CAC_BASE;
-
-		if (cpu_has_mips_r2_r6) {
-			if (cpu_has_ebase_wg) {
-#ifdef CONFIG_64BIT
-				ebase = (read_c0_ebase_64() & ~0xfff);
-#else
-				ebase = (read_c0_ebase() & ~0xfff);
-#endif
-			} else {
-				ebase += (read_c0_ebase() & 0x3ffff000);
-			}
-		}
 	}
 
 	if (cpu_has_mmips) {
-- 
2.21.0

[PATCH 4/4] MIPS: Remove duplicate EBase configuration

[Paul Burton]

Clean up our configuration of the EBase register by making
configure_exception_vector() write to it unconditionally on systems
implementing MIPSr2 or higher, and removing the duplicate code in
per_cpu_trap_init(). The latter would have duplicated work on systems
with vectored interrupts, and didn't set BEV for safety like the
configure_exception_vector() version of the code does.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---
 arch/mips/kernel/traps.c | 20 +++-----------------
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 2775190adbe7..c52766a5b85f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2151,7 +2151,7 @@ static void configure_hwrena(void)
 
 static void configure_exception_vector(void)
 {
-	if (cpu_has_veic || cpu_has_vint) {
+	if (cpu_has_mips_r2_r6) {
 		unsigned long sr = set_c0_status(ST0_BEV);
 		/* If available, use WG to set top bits of EBASE */
 		if (cpu_has_ebase_wg) {
@@ -2163,6 +2163,8 @@ static void configure_exception_vector(void)
 		}
 		write_c0_ebase(ebase);
 		write_c0_status(sr);
+	}
+	if (cpu_has_veic || cpu_has_vint) {
 		/* Setting vector spacing enables EI/VI mode  */
 		change_c0_intctl(0x3e0, VECTORSPACING);
 	}
@@ -2193,22 +2195,6 @@ void per_cpu_trap_init(bool is_boot_cpu)
 	 *  o read IntCtl.IPFDC to determine the fast debug channel interrupt
 	 */
 	if (cpu_has_mips_r2_r6) {
-		/*
-		 * We shouldn't trust a secondary core has a sane EBASE register
-		 * so use the one calculated by the boot CPU.
-		 */
-		if (!is_boot_cpu) {
-			/* If available, use WG to set top bits of EBASE */
-			if (cpu_has_ebase_wg) {
-#ifdef CONFIG_64BIT
-				write_c0_ebase_64(ebase | MIPS_EBASE_WG);
-#else
-				write_c0_ebase(ebase | MIPS_EBASE_WG);
-#endif
-			}
-			write_c0_ebase(ebase);
-		}
-
 		cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
 		cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
 		cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
-- 
2.21.0

[PATCH 3/4] MIPS: Sync icache for whole exception vector

[Paul Burton]

Rather than performing cache flushing for a fixed 0x400 bytes, use the
actual size of the vector in order to ensure we cover all emitted code
on systems that make use of vectored interrupts.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---
 arch/mips/kernel/traps.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9b565ed51662..2775190adbe7 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2454,7 +2454,7 @@ void __init trap_init(void)
 	else
 		set_handler(0x080, &except_vec3_generic, 0x80);
 
-	local_flush_icache_range(ebase, ebase + 0x400);
+	local_flush_icache_range(ebase, ebase + vec_size);
 
 	sort_extable(__start___dbe_table, __stop___dbe_table);
 
-- 
2.21.0

Re: [PATCH 1/4] MIPS: Use memblock_phys_alloc() for exception vector

[Philippe Mathieu-Daudé]

On 5/1/19 12:53 AM, Paul Burton wrote:
> Allocate the exception vector using memblock_phys_alloc() which gives us
> a physical address, rather than the previous convoluted setup which
> obtained a virtual address using memblock_alloc(), converted it to a
> physical address & then back to a virtual address.
> 
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> ---
>  arch/mips/kernel/traps.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 98ca55d62201..00f44b16385e 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -2292,9 +2292,8 @@ void __init trap_init(void)
>  		unsigned long size = 0x200 + VECTORSPACING*64;
>  		phys_addr_t ebase_pa;
>  
> -		ebase = (unsigned long)
> -			memblock_alloc(size, 1 << fls(size));
> -		if (!ebase)
> +		ebase_pa = memblock_phys_alloc(size, 1 << fls(size));
> +		if (!ebase_pa)
>  			panic("%s: Failed to allocate %lu bytes align=0x%x\n",
>  			      __func__, size, 1 << fls(size));
>  
> @@ -2309,9 +2308,10 @@ void __init trap_init(void)
>  		 * EVA is special though as it allows segments to be rearranged
>  		 * and to become uncached during cache error handling.
>  		 */
> -		ebase_pa = __pa(ebase);
>  		if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
>  			ebase = CKSEG0ADDR(ebase_pa);
> +		else
> +			ebase = (unsigned long)phys_to_virt(ebase_pa);
>  	} else {
>  		ebase = CAC_BASE;
>  
> 

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH 3/4] MIPS: Sync icache for whole exception vector

[Philippe Mathieu-Daudé]

On 5/1/19 12:53 AM, Paul Burton wrote:
> Rather than performing cache flushing for a fixed 0x400 bytes, use the
> actual size of the vector in order to ensure we cover all emitted code
> on systems that make use of vectored interrupts.
> 
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> ---
>  arch/mips/kernel/traps.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 9b565ed51662..2775190adbe7 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -2454,7 +2454,7 @@ void __init trap_init(void)
>  	else
>  		set_handler(0x080, &except_vec3_generic, 0x80);
>  
> -	local_flush_icache_range(ebase, ebase + 0x400);
> +	local_flush_icache_range(ebase, ebase + vec_size);
>  
>  	sort_extable(__start___dbe_table, __stop___dbe_table);
>  
> 

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH 0/4] MIPS: Exception vector improvements

[Serge Semin]

On Tue, Apr 30, 2019 at 10:53:29PM +0000, Paul Burton wrote:

Hello Paul 

> This series improves the way we allocate memory for our exception vector
> & configure it in EBase.
> 
> Patch 2 in particular is important preparation for changes being made by
> Serge Semin in his "mips: Post-bootmem-memblock transition fixes"
> series.
> 
> Paul Burton (4):
>   MIPS: Use mnemblock_phys_alloc() for exception vector
>   MIPS: Always allocate exception vector for MIPSr2+
>   MIPS: Sync icache for whole exception vector
>   MIPS: Remove duplicate EBase configuration
> 
>  arch/mips/kernel/traps.c | 63 ++++++++++++++--------------------------
>  1 file changed, 22 insertions(+), 41 deletions(-)
> 
> -- 
> 2.21.0
>

For the whole series:
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
(on kernel 4.9 and Baikal-T1 MIPS P5600 Warrior)

-Sergey

Re: [PATCH 0/4] MIPS: Exception vector improvements

[Paul Burton]

Hello,

Paul Burton wrote:
> This series improves the way we allocate memory for our exception vector
> & configure it in EBase.
> 
> Patch 2 in particular is important preparation for changes being made by
> Serge Semin in his "mips: Post-bootmem-memblock transition fixes"
> series.
> 
> Paul Burton (4):
> MIPS: Use mnemblock_phys_alloc() for exception vector
> MIPS: Always allocate exception vector for MIPSr2+
> MIPS: Sync icache for whole exception vector
> MIPS: Remove duplicate EBase configuration
> 
> arch/mips/kernel/traps.c | 63 ++++++++++++++--------------------------
> 1 file changed, 22 insertions(+), 41 deletions(-)
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> Tested-by: Serge Semin <fancer.lancer@gmail.com>

Series applied to mips-next.

Thanks,
    Paul

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