From: Stephen Boyd <sboyd@kernel.org>
To: "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
Chuanhong Guo <gch981213@gmail.com>,
open list <linux-kernel@vger.kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paul.burton@mips.com>,
James Hogan <jhogan@kernel.org>, John Crispin <john@phrozen.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Weijie Gao <hackpascal@gmail.com>, NeilBrown <neil@brown.name>,
Chuanhong Guo <gch981213@gmail.com>,
Rob Herring <robh@kernel.org>
Subject: Re: [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll
Date: Mon, 22 Jul 2019 14:40:39 -0700 [thread overview]
Message-ID: <20190722214039.E9D9F21951@mail.kernel.org> (raw)
In-Reply-To: <20190709182018.23193-2-gch981213@gmail.com>
The subject of this patch is confusing. Not sure what it has to do with
"MIPS:" so maybe remove that and prefix it "dt-bindings: clock:"
instead.
Quoting Chuanhong Guo (2019-07-09 11:20:14)
> This patch adds dt binding header for mediatek,mt7621-pll
>
> Signed-off-by: Weijie Gao <hackpascal@gmail.com>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Otherwise looks ok to me. Should I apply it to clk tree?
> include/dt-bindings/clock/mt7621-clk.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt7621-clk.h
>
next prev parent reply other threads:[~2019-07-22 21:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 18:20 [PATCH 0/5] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-09 18:20 ` [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-22 21:40 ` Stephen Boyd [this message]
2019-07-09 18:20 ` [PATCH 2/5] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices Chuanhong Guo
2019-07-22 21:50 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 3/5] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
2019-07-22 21:51 ` Stephen Boyd
2019-07-09 18:20 ` [PATCH 4/5] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
2019-07-10 6:46 ` Chuanhong Guo
2019-07-09 18:20 ` [PATCH 5/5] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
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