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From: Chuanhong Guo <gch981213@gmail.com>
To: linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK),
	devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
	FLATTENED DEVICE TREE BINDINGS),
	linux-kernel@vger.kernel.org (open list),
	linux-mips@vger.kernel.org (open list:MIPS),
	devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM)
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Ralf Baechle <ralf@linux-mips.org>,
	Paul Burton <paul.burton@mips.com>,
	James Hogan <jhogan@kernel.org>, John Crispin <john@phrozen.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Weijie Gao <hackpascal@gmail.com>, NeilBrown <neil@brown.name>,
	Chuanhong Guo <gch981213@gmail.com>
Subject: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation
Date: Wed, 24 Jul 2019 10:23:08 +0800	[thread overview]
Message-ID: <20190724022310.28010-5-gch981213@gmail.com> (raw)
In-Reply-To: <20190724022310.28010-1-gch981213@gmail.com>

This commit adds device tree binding documentation for MT7621
PLL controller.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---

Change since v1:
drop useless syscon in compatible string

 .../bindings/clock/mediatek,mt7621-pll.txt     | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
new file mode 100644
index 000000000000..7dcfbd5283e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
@@ -0,0 +1,18 @@
+Binding for Mediatek MT7621 PLL controller
+
+The PLL controller provides the 2 main clocks of the SoC: CPU and BUS.
+
+Required Properties:
+- compatible: has to be "mediatek,mt7621-pll"
+- #clock-cells: has to be one
+
+Optional properties:
+- clock-output-names: should be "cpu", "bus"
+
+Example:
+	pll {
+		compatible = "mediatek,mt7621-pll";
+
+		#clock-cells = <1>;
+		clock-output-names = "cpu", "bus";
+	};
-- 
2.21.0


  parent reply	other threads:[~2019-07-24  2:24 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-24  2:23 [PATCH v2 0/6] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 1/6] dt-bindings: clock: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 2/6] MIPS: ralink: drop ralink_clk_init for mt7621 Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 3/6] MIPS: ralink: add clock device providing cpu/bus clock " Chuanhong Guo
2019-07-24  2:23 ` Chuanhong Guo [this message]
2019-07-29 17:33   ` [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation Paul Burton
2019-08-13 15:51   ` Rob Herring
2019-08-17 14:42     ` Chuanhong Guo
2019-08-17 15:39       ` Oleksij Rempel
2019-08-17 16:22         ` Chuanhong Guo
2019-08-17 18:05           ` Oleksij Rempel
2019-08-18  2:29             ` Chuanhong Guo
2019-08-18  6:10               ` Oleksij Rempel
2019-08-18  7:19                 ` Chuanhong Guo
2019-08-18  7:59                   ` Oleksij Rempel
2019-08-18  8:26                     ` Chuanhong Guo
2019-08-18  8:44                       ` Chuanhong Guo
2019-08-18  9:51                         ` Oleksij Rempel
2019-08-18 10:07                           ` Chuanhong Guo
2019-08-17 15:40       ` Oleksij Rempel
2019-07-24  2:23 ` [PATCH v2 5/6] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 6/6] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo

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