From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com, paul.burton@mips.com, tglx@linutronix.de,
jason@lakedaemon.net, maz@kernel.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.co, devicetree@vger.kernel.org,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH v1 06/18] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC
Date: Fri, 30 Aug 2019 12:32:20 +0800 [thread overview]
Message-ID: <20190830043232.20191-1-jiaxun.yang@flygoat.com> (raw)
Document Loongson-3 I/O Interrupt controller.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
.../loongson,ls3-iointc.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
new file mode 100644
index 000000000000..9aee10abd5cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-iointc.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-iointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt source which can route interrupt to interrupt line of cores.
+
+properties:
+ compatible:
+ const: loongson,ls3-iointc
+
+ reg:
+ maxItems: 1
+
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ description: |
+ Specifies the number of cells needed to encode an interrupt source.
+ Must be 2 or 4.
+ If the system requires describing interrupt line & core mapping, than
+ it must be 4.
+
+ The 1st cell is the hardware interrupt number.
+
+ The 2nd cell is the flags, encoded as follows:
+ bits[3:0] trigger type and level flags.
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive.
+
+ The 3rd is the parent interrupt line that interrupt would map to.
+ As the CPU preserved 4 interrupt lines for I/O, in theory any of the iointc
+ interrupt can be chained to any interrupt lines on a core. But currently
+ we can only map all the interrupt to a single parent, so this cell must be
+ set uniformly for all the child interrupts corresponding to the parent
+ interrupt.
+
+ The 4th is the parent core that interrupt would map to. The interrupt
+ contoller can map any of the interrupt to the specified core on a package.
+ This cell determined the core. It must be the bootcore.
+
+ If the 3rd, 4th cell is not set, it will default to the 0# interrupt line
+ and bootcore.
+
+ enum: [ 2, 4 ]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,ls3-io-intc";
+ reg = <0x3ff01400 0x60>;
+ interrupts = <2>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+...
--
2.22.0
next reply other threads:[~2019-08-30 4:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-30 4:32 Jiaxun Yang [this message]
2019-08-30 4:32 ` [PATCH v1 07/18] irqchip: Add driver for Loongson-3 HyperTransport interrupt controller Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 08/18] dt-bindings: interrupt-controller: Add Loongson-3 HTINTC Jiaxun Yang
2019-09-02 13:39 ` Rob Herring
2019-08-30 4:32 ` [PATCH v1 09/18] irqchip: i8259: Add plat-poll support Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 10/18] irqchip: mips-cpu: Convert to simple domain Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 11/18] MIPS: Loongson64: Drop legacy IRQ code Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 12/18] dt-bindings: mips: Add loongson cpus & boards Jiaxun Yang
2019-09-13 14:36 ` Rob Herring
2019-08-30 4:32 ` [PATCH v1 13/18] dt-bindings: Document loongson vendor-prefix Jiaxun Yang
2019-09-02 13:39 ` Rob Herring
2019-08-30 4:32 ` [PATCH v1 14/18] MIPS: Loongson64: Add generic dts Jiaxun Yang
[not found] ` <tencent_1942EDDF41E4786E357A4E9D@qq.com>
2019-09-04 6:08 ` Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 15/18] MIPS: Loongson64: Load built-in dtbs Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 16/18] MIPS: Loongson: Regenerate defconfigs Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 17/18] MAINTAINERS: Add new pathes to LOONGSON64 ARCHITECTURE Jiaxun Yang
2019-08-30 4:32 ` [PATCH v1 18/18] MAINTAINERS: Add myself as maintainer of LOONGSON64 Jiaxun Yang
2019-09-02 13:38 ` [PATCH v1 06/18] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Rob Herring
-- strict thread matches above, loose matches on Subject: below --
2019-08-30 4:25 [PATCH v1 00/18] Modernize Loongson64 Machine Jiaxun Yang
2019-08-30 4:25 ` [PATCH v1 06/18] dt-bindings: interrupt-controller: Add Loongson-3 IOINTC Jiaxun Yang
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