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From: Paul Burton <paulburton@kernel.org>
To: Huacai Chen <chenhc@lemote.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
	James Hogan <jhogan@kernel.org>,
	Paul Burton <paul.burton@mips.com>,
	linux-mips@linux-mips.org, linux-mips@vger.kernel.org,
	Fuxin Zhang <zhangfx@lemote.com>,
	Zhangjin Wu <wuzhangjin@gmail.com>,
	Huacai Chen <chenhuacai@gmail.com>
Subject: Re: [PATCH V2] MIPS: Loongson: Add board_ebase_setup() support
Date: Fri, 8 Nov 2019 11:11:49 -0800
Message-ID: <20191108191149.bbq3h4xp4famsh2n@lantea.localdomain> (raw)
In-Reply-To: <1572847781-21652-1-git-send-email-chenhc@lemote.com>

Hi Huacai,

On Mon, Nov 04, 2019 at 02:09:41PM +0800, Huacai Chen wrote:
> Old processors before Loongson-3A2000 have a 32bit ebase register and
> have no WG bit, new processors since Loongson-3A2000 have a 64bit ebase
> register and do have the WG bit. Unfortunately, Loongson processors
> which have the WG bit are slightly different from MIPS R2. This makes
> the generic ebase setup not suitable for every scenarios.

Can you describe how the Loongson WG bit differs from the WG bit as
architecturally defined? This patch may make things work for you but it
doesn't give us any record of what the hardware errata is or what we
actually need to do to work with the broken WG bit.

For example - right now Loongson kernels don't use the WG bit at all, so
what's the problem? It doesn't matter if WG has different behavior if we
don't use it.

So one option here might be to just continue to not indicate support for
the WG bit. It does look like the kernel ought to be ensuring the
exception vector it allocates is at a suitable address in this case, and
currently isn't. Something like the (untested) patch below ought to
address that. In practice though memblock is configured to allocate
bottom-up until after this point so it should be unlikely we'll get an
unsuitable address, and there's a WARN_ON() in trap_init() that would
already tell you if that happened.

> To make Loongson's kernel be more robust, we add a board_ebase_setup()
> hook to ensure that CKSEG0 is always used for ebase. This is also useful
> on platforms where BIOS doesn't initialise an appropriate ebase.

Can you also elaborate on that? I'm not sure why this would help on
systems that don't initialize EBase - the kernel unconditionally sets
EBase for >= MIPSr2 systems in configure_exception_vector() anyway, and
since v5.2 it doesn't even try to inherit whatever the bootloader used.

Thanks,
    Paul

---
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 342e41de9d64..a25ee41eff48 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2271,7 +2271,7 @@ void __init trap_init(void)
 	extern char except_vec4;
 	extern char except_vec3_r4000;
 	unsigned long i, vec_size;
-	phys_addr_t ebase_pa;
+	phys_addr_t ebase_pa, ebase_limit;
 
 	check_wait();
 
@@ -2287,7 +2287,21 @@ void __init trap_init(void)
 		else
 			vec_size = PAGE_SIZE;
 
-		ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
+		/*
+		 * If we have support for the EBase.WG bit then allow the
+		 * exception vector to be located anywhere. When EBase.WG is
+		 * not supported EBase is limited to a (c)kseg[01] address, so
+		 * we must ensure the allocated vector is in memory accessible
+		 * via those unmapped regions.
+		 */
+		if (cpu_has_ebase_wg)
+			ebase_limit = MEMBLOCK_ALLOC_ACCESSIBLE;
+		else
+			ebase_limit = CKSEG1 - CKSEG0;
+
+		ebase_pa = memblock_phys_alloc_range(vec_size,
+						     1 << fls(vec_size),
+						     0, ebase_limit);
 		if (!ebase_pa)
 			panic("%s: Failed to allocate %lu bytes align=0x%x\n",
 			      __func__, vec_size, 1 << fls(vec_size));

  parent reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-04  6:09 Huacai Chen
2019-11-07 11:47 ` Jiaxun Yang
2019-11-08  1:21   ` Huacai Chen
2019-11-08 19:11 ` Paul Burton [this message]
2019-11-09 11:02   ` Huacai Chen
2019-11-15  8:22     ` Huacai Chen

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