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From: Paul Burton <paulburton@kernel.org>
To: Christoph Hellwig <hch@lst.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
	James Hogan <jhogan@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	linux-mips@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] MIPS: define ioremap_nocache to ioremap
Date: Mon, 9 Dec 2019 10:46:54 -0800	[thread overview]
Message-ID: <20191209184654.w2d7mguzfc5cyage@lantea.localdomain> (raw)
In-Reply-To: <20191209135823.28465-2-hch@lst.de>

Hi Christoph,

On Mon, Dec 09, 2019 at 02:58:21PM +0100, Christoph Hellwig wrote:
> They are both defined the same way, but this makes it easier to validate
> the scripted ioremap_nocache removal following soon.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>

Acked-by: Paul Burton <paulburton@kernel.org>

Thanks,
    Paul

> ---
>  arch/mips/include/asm/io.h | 25 ++-----------------------
>  1 file changed, 2 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 3f6ce74335b4..d9caa811a2fa 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -227,29 +227,8 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset,
>   */
>  #define ioremap(offset, size)						\
>  	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
> -
> -/*
> - * ioremap_nocache     -   map bus memory into CPU space
> - * @offset:    bus address of the memory
> - * @size:      size of the resource to map
> - *
> - * ioremap_nocache performs a platform specific sequence of operations to
> - * make bus memory CPU accessible via the readb/readw/readl/writeb/
> - * writew/writel functions and the other mmio helpers. The returned
> - * address is not guaranteed to be usable directly as a virtual
> - * address.
> - *
> - * This version of ioremap ensures that the memory is marked uncachable
> - * on the CPU as well as honouring existing caching rules from things like
> - * the PCI bus. Note that there are other caches and buffers on many
> - * busses. In particular driver authors should read up on PCI writes
> - *
> - * It's useful if some control registers are in such an area and
> - * write combining or read caching is not desirable:
> - */
> -#define ioremap_nocache(offset, size)					\
> -	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
> -#define ioremap_uc ioremap_nocache
> +#define ioremap_nocache		ioremap
> +#define ioremap_uc		ioremap
>  
>  /*
>   * ioremap_cache -	map bus memory into CPU space
> -- 
> 2.20.1
> 

  reply	other threads:[~2019-12-09 18:45 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-09 13:58 RFC: kill off ioremap_nocache Christoph Hellwig
2019-12-09 13:58 ` [PATCH 1/2] MIPS: define ioremap_nocache to ioremap Christoph Hellwig
2019-12-09 18:46   ` Paul Burton [this message]
     [not found] ` <20191209135823.28465-3-hch@lst.de>
2019-12-09 15:58   ` [PATCH 2/2] remove ioremap_nocache and devm_ioremap_nocache Arnd Bergmann
2019-12-09 18:48 ` RFC: kill off ioremap_nocache Linus Torvalds
2019-12-09 19:48   ` Christoph Hellwig
2019-12-17 18:35   ` Christoph Hellwig

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