[RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way

[RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way

[Jiaxun Yang]

In [1], we discussed about why MIPS CPU IRQ doesn't fit simple IRQ domain.
I felt it's time to remove this barrier and "modernize" the whole flow.

This set is simply a proof of concept of removing the whole MIPS_CPU_IRQ_BASE
and use the irq_domain's way.

Currently only Loongson64 and ip22 are adapted for testing purpose,
if everybody is happy with it, then I'll take a look at more platforms.

Btw: Thomas, are you still willing to drop some platforms in 5.8?

[1]: https://patchwork.kernel.org/patch/11456911/

Jiaxun Yang (6):
  MIPS: irq_cpu: Add a helper to map virq for CPU IRQ
  irqchip: mips-cpu: Allocate fwnode for non-DT platforms
  irqchip: mips-cpu: Convert to simple domain
  MIPS: kernel: Use mips_cpu_map_virq helper
  MIPS: loongson64: Use mips_cpu_map_virq helper
  MIPS: ip22: Use mips_cpu_map_virq helper

 arch/mips/include/asm/irq_cpu.h      | 19 +++++++++++++++++-
 arch/mips/include/asm/sgi/ip22.h     | 30 ++++++++++++++--------------
 arch/mips/kernel/cevt-r4k.c          |  2 +-
 arch/mips/kernel/perf_event_mipsxx.c |  3 ++-
 arch/mips/kernel/rtlx-mt.c           |  7 +++++--
 arch/mips/loongson64/smp.c           |  6 ++++--
 arch/mips/sgi-ip22/ip22-int.c        | 14 ++++++++-----
 drivers/irqchip/irq-mips-cpu.c       | 22 ++++++++++++++------
 8 files changed, 70 insertions(+), 33 deletions(-)

-- 
2.26.0.rc2

[RFC PATCH 1/6] MIPS: irq_cpu: Add a helper to map virq for CPU IRQ

[Jiaxun Yang]

To care legacy platform without dt, we need this helper
to map virq for cpu_irq in order to deal with legacy drivers
rely on irq number.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/include/asm/irq_cpu.h | 19 ++++++++++++++++++-
 drivers/irqchip/irq-mips-cpu.c  |  8 ++++----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index 83d7331ab215..231c5dc64c19 100644
--- a/arch/mips/include/asm/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -9,12 +9,29 @@
 #ifndef _ASM_IRQ_CPU_H
 #define _ASM_IRQ_CPU_H
 
+#include <linux/irqdomain.h>
+
 extern void mips_cpu_irq_init(void);
+extern struct irq_domain *mips_cpu_irq_domain;
 
 #ifdef CONFIG_IRQ_DOMAIN
-struct device_node;
 extern int mips_cpu_irq_of_init(struct device_node *of_node,
 				struct device_node *parent);
+
+static inline int mips_cpu_map_virq(int hwirq)
+{
+	struct irq_fwspec fwspec;
+
+	fwspec.fwnode = mips_cpu_irq_domain->fwnode;
+	fwspec.param_count = 1;
+	fwspec.param[0] = hwirq;
+	return irq_create_fwspec_mapping(&fwspec);
+}
+#else
+static inline int mips_cpu_map_virq(int hwirq)
+{
+	return MIPS_CPU_IRQ_BASE + hwirq;
+}
 #endif
 
 #endif /* _ASM_IRQ_CPU_H */
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..19734b11b36d 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -34,7 +34,7 @@
 #include <asm/mipsmtregs.h>
 #include <asm/setup.h>
 
-static struct irq_domain *irq_domain;
+struct irq_domain *mips_cpu_irq_domain;
 static struct irq_domain *ipi_domain;
 
 static inline void unmask_mips_irq(struct irq_data *d)
@@ -141,7 +141,7 @@ asmlinkage void __weak plat_irq_dispatch(void)
 		if (IS_ENABLED(CONFIG_GENERIC_IRQ_IPI) && irq < 2)
 			virq = irq_linear_revmap(ipi_domain, irq);
 		else
-			virq = irq_linear_revmap(irq_domain, irq);
+			virq = irq_linear_revmap(mips_cpu_irq_domain, irq);
 		do_IRQ(virq);
 		pending &= ~BIT(irq);
 	}
@@ -251,10 +251,10 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
 
-	irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+	mips_cpu_irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
 					   &mips_cpu_intc_irq_domain_ops,
 					   NULL);
-	if (!irq_domain)
+	if (!mips_cpu_irq_domain)
 		panic("Failed to add irqdomain for MIPS CPU");
 
 	/*
-- 
2.26.0.rc2

[PATCH 1/2] MIPS: Kill MIPS_GIC_IRQ_BASE

[Jiaxun Yang]

It never got used by any driver.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/include/asm/mach-generic/irq.h   | 6 ------
 arch/mips/include/asm/mach-ralink/mt7621.h | 2 --
 2 files changed, 8 deletions(-)

diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index be546a0f65fa..72ac2c202c55 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -36,10 +36,4 @@
 
 #endif /* CONFIG_IRQ_MIPS_CPU */
 
-#ifdef CONFIG_MIPS_GIC
-#ifndef MIPS_GIC_IRQ_BASE
-#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
-#endif
-#endif /* CONFIG_MIPS_GIC */
-
 #endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
index 65483a4681ab..e1af1ba50bd8 100644
--- a/arch/mips/include/asm/mach-ralink/mt7621.h
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -31,6 +31,4 @@
 #define MT7621_CHIP_NAME0		0x3637544D
 #define MT7621_CHIP_NAME1		0x20203132
 
-#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)
-
 #endif
-- 
2.26.0.rc2

[RFC PATCH 2/6] irqchip: mips-cpu: Allocate fwnode for non-DT platforms

[Jiaxun Yang]

fwnode is required by fwspec based domain opreations to match domains.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 drivers/irqchip/irq-mips-cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 19734b11b36d..e029e0fe2ee2 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -247,6 +247,8 @@ static inline void mips_cpu_register_ipi_domain(struct device_node *of_node) {}
 
 static void __init __mips_cpu_irq_init(struct device_node *of_node)
 {
+	struct fwnode_handle *fwnode;
+
 	/* Mask interrupts. */
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
@@ -257,6 +259,14 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
 	if (!mips_cpu_irq_domain)
 		panic("Failed to add irqdomain for MIPS CPU");
 
+	if (!of_node) {
+		fwnode = irq_domain_alloc_named_fwnode("MIPS-CPU-IRQ");
+		if (!fwnode)
+			panic("Failed to allocate fwnode for MIPS CPU IRQ");
+		mips_cpu_irq_domain->fwnode = fwnode;
+		mips_cpu_irq_domain->name = kstrdup("MIPS-CPU-IRQ", GFP_KERNEL);
+	}
+
 	/*
 	 * Only proceed to register the software interrupt IPI implementation
 	 * for CPUs which implement the MIPS MT (multi-threading) ASE.
-- 
2.26.0.rc2

[PATCH 2/2] MIPS: Kill RM7K & RM9K IRQ Code

[Jiaxun Yang]

RM7000 IRQ driver never got really used by any of the platform,
and rm9k_cpu_irq_init only exist in a header.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/Kconfig                        |  3 --
 arch/mips/include/asm/irq_cpu.h          |  2 --
 arch/mips/include/asm/mach-generic/irq.h |  6 ----
 arch/mips/kernel/Makefile                |  1 -
 arch/mips/kernel/irq-rm7000.c            | 45 ------------------------
 5 files changed, 57 deletions(-)
 delete mode 100644 arch/mips/kernel/irq-rm7000.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a1f973cc0265..7cda047766bd 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1309,9 +1309,6 @@ config SYS_SUPPORTS_HUGETLBFS
 config MIPS_HUGE_TLB_SUPPORT
 	def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
 
-config IRQ_CPU_RM7K
-	bool
-
 config IRQ_MSP_SLP
 	bool
 
diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index 8d321180b5c2..83d7331ab215 100644
--- a/arch/mips/include/asm/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -10,8 +10,6 @@
 #define _ASM_IRQ_CPU_H
 
 extern void mips_cpu_irq_init(void);
-extern void rm7k_cpu_irq_init(void);
-extern void rm9k_cpu_irq_init(void);
 
 #ifdef CONFIG_IRQ_DOMAIN
 struct device_node;
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index 72ac2c202c55..ac711b0d6225 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -28,12 +28,6 @@
 #endif /* CONFIG_I8259 */
 #endif
 
-#ifdef CONFIG_IRQ_CPU_RM7K
-#ifndef RM7K_CPU_IRQ_BASE
-#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
-#endif
-#endif
-
 #endif /* CONFIG_IRQ_MIPS_CPU */
 
 #endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index d6e97df51cfb..c0a7e3f266e1 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -64,7 +64,6 @@ obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
 obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o
 obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o
 
-obj-$(CONFIG_IRQ_CPU_RM7K)	+= irq-rm7000.o
 obj-$(CONFIG_MIPS_MSC)		+= irq-msc01.o
 obj-$(CONFIG_IRQ_TXX9)		+= irq_txx9.o
 obj-$(CONFIG_IRQ_GT641XX)	+= irq-gt641xx.o
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
deleted file mode 100644
index e1a497f639d7..000000000000
--- a/arch/mips/kernel/irq-rm7000.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2003 Ralf Baechle
- *
- * Handler for RM7000 extended interrupts.  These are a non-standard
- * feature so we handle them separately from standard interrupts.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-
-static inline void unmask_rm7k_irq(struct irq_data *d)
-{
-	set_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE));
-}
-
-static inline void mask_rm7k_irq(struct irq_data *d)
-{
-	clear_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE));
-}
-
-static struct irq_chip rm7k_irq_controller = {
-	.name = "RM7000",
-	.irq_ack = mask_rm7k_irq,
-	.irq_mask = mask_rm7k_irq,
-	.irq_mask_ack = mask_rm7k_irq,
-	.irq_unmask = unmask_rm7k_irq,
-	.irq_eoi = unmask_rm7k_irq
-};
-
-void __init rm7k_cpu_irq_init(void)
-{
-	int base = RM7K_CPU_IRQ_BASE;
-	int i;
-
-	clear_c0_intcontrol(0x00000f00);		/* Mask all */
-
-	for (i = base; i < base + 4; i++)
-		irq_set_chip_and_handler(i, &rm7k_irq_controller,
-					 handle_percpu_irq);
-}
-- 
2.26.0.rc2

[RFC PATCH 3/6] irqchip: mips-cpu: Convert to simple domain

[Jiaxun Yang]

This would be the first step of remove MIPS_CPU_IRQ_BASE
tree wide.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 drivers/irqchip/irq-mips-cpu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index e029e0fe2ee2..ab57003ace5b 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -253,9 +253,9 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node)
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
 
-	mips_cpu_irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
-					   &mips_cpu_intc_irq_domain_ops,
-					   NULL);
+	mips_cpu_irq_domain = irq_domain_add_simple(of_node, 8, 0,
+				&mips_cpu_intc_irq_domain_ops, NULL);
+
 	if (!mips_cpu_irq_domain)
 		panic("Failed to add irqdomain for MIPS CPU");
 
-- 
2.26.0.rc2

[RFC PATCH 4/6] MIPS: kernel: Use mips_cpu_map_virq helper

[Jiaxun Yang]

Remove the use of MIPS_CPU_IRQ_BASE and step forward
to purely irq domain based platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/kernel/cevt-r4k.c          | 2 +-
 arch/mips/kernel/perf_event_mipsxx.c | 3 ++-
 arch/mips/kernel/rtlx-mt.c           | 7 +++++--
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 17a9cbb8b3df..d838b1cad0f7 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -247,7 +247,7 @@ int c0_compare_int_usable(void)
 
 unsigned int __weak get_c0_compare_int(void)
 {
-	return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+	return mips_cpu_map_virq(p0_compare_irq);
 }
 
 int r4k_clockevent_init(void)
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 128fc9999c56..8fc484fe8afa 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -20,6 +20,7 @@
 #include <linux/uaccess.h>
 
 #include <asm/irq.h>
+#include <asm/irq_cpu.h>
 #include <asm/irq_regs.h>
 #include <asm/stacktrace.h>
 #include <asm/time.h> /* For perf_irq */
@@ -1702,7 +1703,7 @@ init_hw_perf_events(void)
 	if (get_c0_perfcount_int)
 		irq = get_c0_perfcount_int();
 	else if (cp0_perfcount_irq >= 0)
-		irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+		irq = mips_cpu_map_virq(cp0_perfcount_irq);
 	else
 		irq = -1;
 
diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c
index 38c6925a1bea..110ed768d2ef 100644
--- a/arch/mips/kernel/rtlx-mt.c
+++ b/arch/mips/kernel/rtlx-mt.c
@@ -16,14 +16,17 @@
 
 #include <asm/mips_mt.h>
 #include <asm/vpe.h>
+#include <asm/irq_cpu.h>
 #include <asm/rtlx.h>
 
 static int major;
 
 static void rtlx_dispatch(void)
 {
-	if (read_c0_cause() & read_c0_status() & C_SW0)
-		do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
+	if (read_c0_cause() & read_c0_status() & C_SW0) {
+		do_IRQ(irq_linear_revmap(mips_cpu_irq_domain,
+						MIPS_CPU_RTLX_IRQ);
+	}
 }
 
 /*
-- 
2.26.0.rc2

[RFC PATCH 5/6] MIPS: loongson64: Use mips_cpu_map_virq helper

[Jiaxun Yang]

Remove the use of MIPS_CPU_IRQ_BASE and step forward
to purely irq domain based platform.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/loongson64/smp.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e1fe8bbb377d..04ee27baea19 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -18,6 +18,7 @@
 #include <asm/clock.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
+#include <asm/irq_cpu.h>
 #include <loongson.h>
 #include <loongson_regs.h>
 #include <workarounds.h>
@@ -26,7 +27,7 @@
 
 DEFINE_PER_CPU(int, cpu_state);
 
-#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
+#define LS_IPI_IRQ 6
 
 static void *ipi_set0_regs[16];
 static void *ipi_clear0_regs[16];
@@ -428,7 +429,8 @@ static void __init loongson3_smp_setup(void)
 
 static void __init loongson3_prepare_cpus(unsigned int max_cpus)
 {
-	if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt,
+	if (request_irq(mips_cpu_map_virq(LS_IPI_IRQ),
+			loongson3_ipi_interrupt,
 			IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL))
 		pr_err("Failed to request IPI IRQ\n");
 	init_cpu_present(cpu_possible_mask);
-- 
2.26.0.rc2

[RFC PATCH 6/6] MIPS: ip22: Use mips_cpu_map_virq helper

[Jiaxun Yang]

Remove the use of MIPS_CPU_IRQ_BASE and step forward
to purely irq domain based platform.

I'm not brave enough to touch legacy IRQ layout so just
keep it as is.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/include/asm/sgi/ip22.h | 30 +++++++++++++++---------------
 arch/mips/sgi-ip22/ip22-int.c    | 14 +++++++++-----
 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h
index 87ec9eaa04e3..42dadb1d08b8 100644
--- a/arch/mips/include/asm/sgi/ip22.h
+++ b/arch/mips/include/asm/sgi/ip22.h
@@ -24,27 +24,27 @@
 #include <irq.h>
 #include <asm/sgi/ioc.h>
 
+/* 8 MIPS CPU IRQ Lines */
+#define SGI_SOFT_0_IRQ	0
+#define SGI_SOFT_1_IRQ	1
+#define SGI_LOCAL_0_IRQ 2
+#define SGI_LOCAL_1_IRQ 3
+#define SGI_8254_0_IRQ	4
+#define SGI_8254_1_IRQ	5
+#define SGI_BUSERR_IRQ	6
+#define SGI_TIMER_IRQ	7
+
 #define SGINT_EISA	0	/* 16 EISA irq levels (Indigo2) */
-#define SGINT_CPU	MIPS_CPU_IRQ_BASE	/* MIPS CPU define 8 interrupt sources */
-#define SGINT_LOCAL0	(SGINT_CPU+8)	/* 8 local0 irq levels */
-#define SGINT_LOCAL1	(SGINT_CPU+16)	/* 8 local1 irq levels */
-#define SGINT_LOCAL2	(SGINT_CPU+24)	/* 8 local2 vectored irq levels */
-#define SGINT_LOCAL3	(SGINT_CPU+32)	/* 8 local3 vectored irq levels */
-#define SGINT_END	(SGINT_CPU+40)	/* End of 'spaces' */
+#define SGINT_LOCAL0	(SGINT_EISA+24)	/* 8 local0 irq levels */
+#define SGINT_LOCAL1	(SGINT_LOCAL0+8)	/* 8 local1 irq levels */
+#define SGINT_LOCAL2	(SGINT_LOCAL1+8)	/* 8 local2 vectored irq levels */
+#define SGINT_LOCAL3	(SGINT_LOCAL0+8)	/* 8 local3 vectored irq levels */
+#define SGINT_END	(SGINT_LOCAL0+8)	/* End of 'spaces' */
 
 /*
  * Individual interrupt definitions for the Indy and Indigo2
  */
 
-#define SGI_SOFT_0_IRQ	SGINT_CPU + 0
-#define SGI_SOFT_1_IRQ	SGINT_CPU + 1
-#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
-#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
-#define SGI_8254_0_IRQ	SGINT_CPU + 4
-#define SGI_8254_1_IRQ	SGINT_CPU + 5
-#define SGI_BUSERR_IRQ	SGINT_CPU + 6
-#define SGI_TIMER_IRQ	SGINT_CPU + 7
-
 #define SGI_FIFO_IRQ	SGINT_LOCAL0 + 0	/* FIFO full */
 #define SGI_GIO_0_IRQ	SGI_FIFO_IRQ		/* GIO-0 */
 #define SGI_WD93_0_IRQ	SGINT_LOCAL0 + 1	/* 1st onboard WD93 */
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 96798a4ab2de..b1fbd7c5df9d 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -151,7 +151,7 @@ extern void ip22_be_interrupt(int irq);
 
 static void __irq_entry indy_buserror_irq(void)
 {
-	int irq = SGI_BUSERR_IRQ;
+	int irq = mips_cpu_map_virq(SGI_BUSERR_IRQ);
 
 	irq_enter();
 	kstat_incr_irq_this_cpu(irq);
@@ -203,7 +203,8 @@ asmlinkage void plat_irq_dispatch(void)
 	 * First we check for r4k counter/timer IRQ.
 	 */
 	if (pending & CAUSEF_IP7)
-		do_IRQ(SGI_TIMER_IRQ);
+		do_IRQ(irq_linear_revmap(mips_cpu_irq_domain,
+					SGI_TIMER_IRQ));
 	else if (pending & CAUSEF_IP2)
 		indy_local0_irqdispatch();
 	else if (pending & CAUSEF_IP3)
@@ -293,13 +294,16 @@ void __init arch_init_irq(void)
 	}
 
 	/* vector handler. this register the IRQ as non-sharable */
-	if (request_irq(SGI_LOCAL_0_IRQ, no_action, IRQF_NO_THREAD,
+	if (request_irq(mips_cpu_map_virq(SGI_LOCAL_0_IRQ),
+			no_action, IRQF_NO_THREAD,
 			"local0 cascade", NULL))
 		pr_err("Failed to register local0 cascade interrupt\n");
-	if (request_irq(SGI_LOCAL_1_IRQ, no_action, IRQF_NO_THREAD,
+	if (request_irq(mips_cpu_map_virq(SGI_LOCAL_1_IRQ),
+			no_action, IRQF_NO_THREAD,
 			"local1 cascade", NULL))
 		pr_err("Failed to register local1 cascade interrupt\n");
-	if (request_irq(SGI_BUSERR_IRQ, no_action, IRQF_NO_THREAD,
+	if (request_irq(mips_cpu_map_virq(SGI_BUSERR_IRQ),
+			no_action, IRQF_NO_THREAD,
 			"Bus Error", NULL))
 		pr_err("Failed to register Bus Error interrupt\n");
 
-- 
2.26.0.rc2

Re: [RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way

[Thomas Bogendoerfer]

On Thu, Mar 26, 2020 at 02:16:56PM +0800, Jiaxun Yang wrote:
> In [1], we discussed about why MIPS CPU IRQ doesn't fit simple IRQ domain.
> I felt it's time to remove this barrier and "modernize" the whole flow.
> 
> This set is simply a proof of concept of removing the whole MIPS_CPU_IRQ_BASE
> and use the irq_domain's way.
> 
> Currently only Loongson64 and ip22 are adapted for testing purpose,
> if everybody is happy with it, then I'll take a look at more platforms.
> 
> Btw: Thomas, are you still willing to drop some platforms in 5.8?

yes, I didn't receive feedback to not drop them. So after merge
window is over I'm going to post a patch to remove LASAT, NEC_MARKEINS
and PMC_MSP.

>  arch/mips/include/asm/irq_cpu.h      | 19 +++++++++++++++++-
>  arch/mips/include/asm/sgi/ip22.h     | 30 ++++++++++++++--------------
>  arch/mips/kernel/cevt-r4k.c          |  2 +-
>  arch/mips/kernel/perf_event_mipsxx.c |  3 ++-
>  arch/mips/kernel/rtlx-mt.c           |  7 +++++--
>  arch/mips/loongson64/smp.c           |  6 ++++--
>  arch/mips/sgi-ip22/ip22-int.c        | 14 ++++++++-----
>  drivers/irqchip/irq-mips-cpu.c       | 22 ++++++++++++++------
>  8 files changed, 70 insertions(+), 33 deletions(-)

Adding more code for doing the same thing doesn't sound like the
best approach. Is there a big need for that change (like someone
getting rid of irq_domain_add_legacy) ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [RFC PATCH 0/6] MIPS: Handle CPU IRQ in domain's way

[Marc Zyngier]

On 2020-03-26 15:38, Thomas Bogendoerfer wrote:
> On Thu, Mar 26, 2020 at 02:16:56PM +0800, Jiaxun Yang wrote:
>> In [1], we discussed about why MIPS CPU IRQ doesn't fit simple IRQ 
>> domain.
>> I felt it's time to remove this barrier and "modernize" the whole 
>> flow.
>> 
>> This set is simply a proof of concept of removing the whole 
>> MIPS_CPU_IRQ_BASE
>> and use the irq_domain's way.
>> 
>> Currently only Loongson64 and ip22 are adapted for testing purpose,
>> if everybody is happy with it, then I'll take a look at more 
>> platforms.
>> 
>> Btw: Thomas, are you still willing to drop some platforms in 5.8?
> 
> yes, I didn't receive feedback to not drop them. So after merge
> window is over I'm going to post a patch to remove LASAT, NEC_MARKEINS
> and PMC_MSP.
> 
>>  arch/mips/include/asm/irq_cpu.h      | 19 +++++++++++++++++-
>>  arch/mips/include/asm/sgi/ip22.h     | 30 
>> ++++++++++++++--------------
>>  arch/mips/kernel/cevt-r4k.c          |  2 +-
>>  arch/mips/kernel/perf_event_mipsxx.c |  3 ++-
>>  arch/mips/kernel/rtlx-mt.c           |  7 +++++--
>>  arch/mips/loongson64/smp.c           |  6 ++++--
>>  arch/mips/sgi-ip22/ip22-int.c        | 14 ++++++++-----
>>  drivers/irqchip/irq-mips-cpu.c       | 22 ++++++++++++++------
>>  8 files changed, 70 insertions(+), 33 deletions(-)
> 
> Adding more code for doing the same thing doesn't sound like the
> best approach. Is there a big need for that change (like someone
> getting rid of irq_domain_add_legacy) ?

I have no plan to remove the API overnight, but if you guys start
modernizing MIPS, I could be tempted...

         M.
-- 
Jazz is not dead. It just smells funny...