From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5FD1C433E1 for ; Tue, 14 Jul 2020 14:15:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 84FC622510 for ; Tue, 14 Jul 2020 14:15:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725931AbgGNOPJ (ORCPT ); Tue, 14 Jul 2020 10:15:09 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:33610 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725890AbgGNOPJ (ORCPT ); Tue, 14 Jul 2020 10:15:09 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id A21E68030867; Tue, 14 Jul 2020 14:15:06 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3m-kbe7wnLov; Tue, 14 Jul 2020 17:15:06 +0300 (MSK) Date: Tue, 14 Jul 2020 17:15:04 +0300 From: Serge Semin To: Arnd Bergmann CC: Serge Semin , Thomas Gleixner , "Rafael J. Wysocki" , Daniel Lezcano , Thomas Bogendoerfer , Greg Kroah-Hartman , Alexey Malahov , Rob Herring , Jason Cooper , Marc Zyngier , James Hogan , "open list:BROADCOM NVRAM DRIVER" , DTML , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v5 5/6] bus: cdmm: Add MIPS R5 arch support Message-ID: <20200714141504.oybqzaii5hcdy7cq@mobilestation> References: <20200714125753.22466-1-Sergey.Semin@baikalelectronics.ru> <20200714125753.22466-6-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Tue, Jul 14, 2020 at 03:28:30PM +0200, Arnd Bergmann wrote: > On Tue, Jul 14, 2020 at 2:58 PM Serge Semin > wrote: > > > > config MIPS_CDMM > > bool "MIPS Common Device Memory Map (CDMM) Driver" > > - depends on CPU_MIPSR2 > > + depends on CPU_MIPSR2 || CPU_MIPSR5 > > help > > Wouldn't a kernel built for P5600 have CPU_MIPSR2 set already? No. P5600 core is based on MIPS32 r5, for which since 5.8 there has been a dedicated kernel config CPU_MIPSR5 available. > I thought R5 was just a backwards-compatible extension of R2. Yes, it's an extension and they are compatible in most of aspects, but there are still differences, which when activated/used make kernel built for R5 being incompatible with R2. For instance there is an ISA extension in R5 which hasn't been available in R5 like "eretnc" (return from exceptions with no atomic flag cleared), "mfhc/mthc0" (extended C0 register move instructions), etc. There is some other features/optimizations available since R5. Please see commit ab7c01fdc3cf ("mips: Add MIPS Release 5 support") for details. > > If not, what about R3? Currently if some chip is equipped with R3, then the kernel must be built for R2 with features like EVA enabled if it's required. -Sergey > > Arnd