* [PATCH 1/4] MIPS: Loongson64: Fix machine naming
@ 2020-07-09 11:33 Huacai Chen
2020-07-09 11:33 ` [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH Huacai Chen
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Huacai Chen @ 2020-07-09 11:33 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang,
Huacai Chen
From previous commits, the machine names with "loongson3-" prefix have
renamed to "loongson64c-" prefix in documents, but the .dts files have
not been updated as well. So fix it.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts | 2 +-
arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
index acd53a1..d681a29 100644
--- a/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
+++ b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
@@ -6,7 +6,7 @@
#include "rs780e-pch.dtsi"
/ {
- compatible = "loongson,loongson3-4core-rs780e";
+ compatible = "loongson,loongson64c-4core-rs780e";
};
&package0 {
diff --git a/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
index 433f9c3..3c20441 100644
--- a/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
+++ b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
@@ -6,7 +6,7 @@
#include "rs780e-pch.dtsi"
/ {
- compatible = "loongson,loongson3-8core-rs780e";
+ compatible = "loongson,loongson64c-8core-rs780e";
};
&package0 {
--
2.7.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH
2020-07-09 11:33 [PATCH 1/4] MIPS: Loongson64: Fix machine naming Huacai Chen
@ 2020-07-09 11:33 ` Huacai Chen
2020-07-14 7:26 ` Tiezhu Yang
2020-07-16 10:01 ` Thomas Bogendoerfer
2020-07-09 11:33 ` [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs Huacai Chen
` (3 subsequent siblings)
4 siblings, 2 replies; 15+ messages in thread
From: Huacai Chen @ 2020-07-09 11:33 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang,
Huacai Chen
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and
Generic Loongson64 Quad Core + LS7A boards.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/boot/dts/loongson/Makefile | 5 +-
.../boot/dts/loongson/loongson64c_4core_ls7a.dts | 37 ++
.../boot/dts/loongson/loongson64g-package.dtsi | 61 ++++
.../boot/dts/loongson/loongson64g_4core_ls7a.dts | 37 ++
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 371 +++++++++++++++++++++
.../include/asm/mach-loongson64/builtin_dtbs.h | 2 +
6 files changed, 512 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson64g-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
index aa5069a..ae1c8bf 100644
--- a/arch/mips/boot/dts/loongson/Makefile
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -1,4 +1,7 @@
# SPDX_License_Identifier: GPL_2.0
-dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb loongson64c_8core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
new file mode 100644
index 00000000..c7ea4f1c
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson64c-package.dtsi"
+#include "ls7a-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson64c-4core-ls7a";
+};
+
+&package0 {
+ htvec: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htvec-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&pch {
+ msi: msi-controller@2ff00000 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0 0x2ff00000 0 0x8>;
+ interrupt-controller;
+ msi-controller;
+ loongson,msi-base-vec = <64>;
+ loongson,msi-num-vecs = <64>;
+ interrupt-parent = <&htvec>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64g-package.dtsi b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi
new file mode 100644
index 00000000..38abc57
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package0: bus@1fe00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
+
+ liointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0x00ffffff>, /* int0 */
+ <0xff000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0 0x1fe00100 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x1fe00110 0x10>;
+ clock-frequency = <100000000>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&liointc>;
+ no-loopback-test;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
new file mode 100644
index 00000000..bdc911e
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson64g-package.dtsi"
+#include "ls7a-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson64g-4core-ls7a";
+};
+
+&package0 {
+ htvec: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htvec-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&pch {
+ msi: msi-controller@2ff00000 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0 0x2ff00000 0 0x8>;
+ interrupt-controller;
+ msi-controller;
+ loongson,msi-base-vec = <64>;
+ loongson,msi-num-vecs = <128>;
+ interrupt-parent = <&htvec>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
new file mode 100644
index 00000000..1c286bb
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ pch: bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
+ 0 0x20000000 0 0x20000000 0 0x10000000
+ 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
+ 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
+
+ pic: interrupt-controller@10000000 {
+ compatible = "loongson,pch-pic-1.0";
+ reg = <0 0x10000000 0 0x400>;
+ interrupt-controller;
+ interrupt-parent = <&htvec>;
+ loongson,pic-base-vec = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ pci@1a000000 {
+ compatible = "loongson,ls7a-pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <2>;
+ msi-parent = <&msi>;
+
+ reg = <0 0x1a000000 0 0x02000000>,
+ <0xefe 0x00000000 0 0x20000000>;
+
+ ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
+ <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+
+ ohci@4,0 {
+ compatible = "pci0014,7a24.0",
+ "pci0014,7a24",
+ "pciclass0c0310",
+ "pciclass0c03";
+
+ reg = <0x2000 0x0 0x0 0x0 0x0>;
+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ ehci@4,1 {
+ compatible = "pci0014,7a14.0",
+ "pci0014,7a14",
+ "pciclass0c0320",
+ "pciclass0c03";
+
+ reg = <0x2100 0x0 0x0 0x0 0x0>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ ohci@5,0 {
+ compatible = "pci0014,7a24.0",
+ "pci0014,7a24",
+ "pciclass0c0310",
+ "pciclass0c03";
+
+ reg = <0x2800 0x0 0x0 0x0 0x0>;
+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ ehci@5,1 {
+ compatible = "pci0014,7a14.0",
+ "pci0014,7a14",
+ "pciclass0c0320",
+ "pciclass0c03";
+
+ reg = <0x2900 0x0 0x0 0x0 0x0>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ sata@8,0 {
+ compatible = "pci0014,7a08.0",
+ "pci0014,7a08",
+ "pciclass010601",
+ "pciclass0106";
+
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ sata@8,1 {
+ compatible = "pci0014,7a08.0",
+ "pci0014,7a08",
+ "pciclass010601",
+ "pciclass0106";
+
+ reg = <0x4100 0x0 0x0 0x0 0x0>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ sata@8,2 {
+ compatible = "pci0014,7a08.0",
+ "pci0014,7a08",
+ "pciclass010601",
+ "pciclass0106";
+
+ reg = <0x4200 0x0 0x0 0x0 0x0>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ gpu@6,0 {
+ compatible = "pci0014,7a15.0",
+ "pci0014,7a15",
+ "pciclass030200",
+ "pciclass0302";
+
+ reg = <0x3000 0x0 0x0 0x0 0x0>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ dc@6,1 {
+ compatible = "pci0014,7a06.0",
+ "pci0014,7a06",
+ "pciclass030000",
+ "pciclass0300";
+
+ reg = <0x3100 0x0 0x0 0x0 0x0>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ hda@7,0 {
+ compatible = "pci0014,7a07.0",
+ "pci0014,7a07",
+ "pciclass040300",
+ "pciclass0403";
+
+ reg = <0x3800 0x0 0x0 0x0 0x0>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ gmac@3,0 {
+ compatible = "pci0014,7a03.0",
+ "pci0014,7a03",
+ "pciclass020000",
+ "pciclass0200";
+
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ interrupt-parent = <&pic>;
+ phy-mode = "rgmii";
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ gmac@3,1 {
+ compatible = "pci0014,7a03.0",
+ "pci0014,7a03",
+ "pciclass020000",
+ "pciclass0200";
+
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ interrupt-parent = <&pic>;
+ phy-mode = "rgmii";
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+ };
+
+ pci_bridge@9,0 {
+ compatible = "pci0014,7a19.1",
+ "pci0014,7a19",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@a,0 {
+ compatible = "pci0014,7a09.1",
+ "pci0014,7a09",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x5000 0x0 0x0 0x0 0x0>;
+ interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@b,0 {
+ compatible = "pci0014,7a09.1",
+ "pci0014,7a09",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@c,0 {
+ compatible = "pci0014,7a09.1",
+ "pci0014,7a09",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x6000 0x0 0x0 0x0 0x0>;
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@d,0 {
+ compatible = "pci0014,7a19.1",
+ "pci0014,7a19",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@e,0 {
+ compatible = "pci0014,7a09.1",
+ "pci0014,7a09",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x7000 0x0 0x0 0x0 0x0>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@f,0 {
+ compatible = "pci0014,7a29.1",
+ "pci0014,7a29",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x7800 0x0 0x0 0x0 0x0>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@10,0 {
+ compatible = "pci0014,7a19.1",
+ "pci0014,7a19",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x8000 0x0 0x0 0x0 0x0>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@11,0 {
+ compatible = "pci0014,7a29.1",
+ "pci0014,7a29",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x8800 0x0 0x0 0x0 0x0>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@12,0 {
+ compatible = "pci0014,7a19.1",
+ "pci0014,7a19",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x9000 0x0 0x0 0x0 0x0>;
+ interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@13,0 {
+ compatible = "pci0014,7a29.1",
+ "pci0014,7a29",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x9800 0x0 0x0 0x0 0x0>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@14,0 {
+ compatible = "pci0014,7a19.1",
+ "pci0014,7a19",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0xa000 0x0 0x0 0x0 0x0>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
index 930c8a1..6d2f141 100644
--- a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -8,6 +8,8 @@
#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
+extern u32 __dtb_loongson64c_4core_ls7a_begin[];
extern u32 __dtb_loongson64c_4core_rs780e_begin[];
extern u32 __dtb_loongson64c_8core_rs780e_begin[];
+extern u32 __dtb_loongson64g_4core_ls7a_begin[];
#endif
--
2.7.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs
2020-07-09 11:33 [PATCH 1/4] MIPS: Loongson64: Fix machine naming Huacai Chen
2020-07-09 11:33 ` [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH Huacai Chen
@ 2020-07-09 11:33 ` Huacai Chen
2020-07-14 7:27 ` Tiezhu Yang
2020-07-16 10:01 ` Thomas Bogendoerfer
2020-07-09 11:33 ` [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type Huacai Chen
` (2 subsequent siblings)
4 siblings, 2 replies; 15+ messages in thread
From: Huacai Chen @ 2020-07-09 11:33 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang,
Huacai Chen
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Load correct devicetree according to PRID and PCH type.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/loongson64/env.c | 56 ++++++++++++++++++++++++++++------------------
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 3e7caba..2cb9573 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -126,28 +126,6 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
- if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
- switch (read_c0_prid() & PRID_REV_MASK) {
- case PRID_REV_LOONGSON3A_R1:
- case PRID_REV_LOONGSON3A_R2_0:
- case PRID_REV_LOONGSON3A_R2_1:
- case PRID_REV_LOONGSON3A_R3_0:
- case PRID_REV_LOONGSON3A_R3_1:
- loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
- break;
- case PRID_REV_LOONGSON3B_R1:
- case PRID_REV_LOONGSON3B_R2:
- loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
- break;
- default:
- break;
- }
- }
-
-
- if (!loongson_fdt_blob)
- pr_err("Failed to determine built-in Loongson64 dtb\n");
-
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
@@ -198,4 +176,38 @@ void __init prom_init_env(void)
loongson_sysconf.bridgetype = RS780E;
loongson_sysconf.early_config = rs780e_early_config;
}
+
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ switch (loongson_sysconf.bridgetype) {
+ case LS7A:
+ loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
+ break;
+ case RS780E:
+ loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ if (loongson_sysconf.bridgetype == RS780E)
+ loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
+ if (loongson_sysconf.bridgetype == LS7A)
+ loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
+ }
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
}
--
2.7.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type
2020-07-09 11:33 [PATCH 1/4] MIPS: Loongson64: Fix machine naming Huacai Chen
2020-07-09 11:33 ` [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH Huacai Chen
2020-07-09 11:33 ` [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs Huacai Chen
@ 2020-07-09 11:33 ` Huacai Chen
2020-07-14 7:27 ` Tiezhu Yang
2020-07-16 10:00 ` Thomas Bogendoerfer
2020-07-14 7:25 ` [PATCH 1/4] MIPS: Loongson64: Fix machine naming Tiezhu Yang
2020-07-16 10:00 ` Thomas Bogendoerfer
4 siblings, 2 replies; 15+ messages in thread
From: Huacai Chen @ 2020-07-09 11:33 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang,
Huacai Chen
Define MMIO_LOWER_RESERVED as a constant is incorrect, because different
PCHs (bridge types) have different legacy MMIO space size. According to
the datasheets, the legacy MMIO space size of LS7A is 0x20000, and which
of other PCHs is 0x4000. So it is necessary to reserve legacy MMIO space
according to the bridge type.
Currently IO_SPACE_LIMIT is defined as 0xffff which is too small for the
LS7A bridge, so increase it to 0xfffff for LOONGSON64.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/io.h | 4 ++++
arch/mips/include/asm/mach-loongson64/spaces.h | 3 ---
arch/mips/loongson64/init.c | 18 ++++++++++++++----
3 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 346fffd..7358372 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -51,7 +51,11 @@
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
+#ifndef CONFIG_CPU_LOONGSON64
#define IO_SPACE_LIMIT 0xffff
+#else
+#define IO_SPACE_LIMIT 0xfffff
+#endif
/*
* On MIPS I/O ports are memory mapped, so we access them using normal
diff --git a/arch/mips/include/asm/mach-loongson64/spaces.h b/arch/mips/include/asm/mach-loongson64/spaces.h
index 3de0ac9..93bdd9e 100644
--- a/arch/mips/include/asm/mach-loongson64/spaces.h
+++ b/arch/mips/include/asm/mach-loongson64/spaces.h
@@ -11,8 +11,5 @@
#define PCI_IOSIZE SZ_16M
#define MAP_BASE (PCI_IOBASE + PCI_IOSIZE)
-/* Reserved at the start of PCI_IOBASE for legacy drivers */
-#define MMIO_LOWER_RESERVED 0x10000
-
#include <asm/mach-generic/spaces.h>
#endif
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 59ddada..606cdc4 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -65,14 +65,25 @@ void __init prom_free_prom_memory(void)
static __init void reserve_pio_range(void)
{
+ /* Reserved at the start of PCI_IOBASE for legacy drivers */
+ int mmio_lower_reserved;
struct logic_pio_hwaddr *range;
range = kzalloc(sizeof(*range), GFP_ATOMIC);
if (!range)
return;
+ switch (loongson_sysconf.bridgetype) {
+ case LS7A:
+ mmio_lower_reserved = 0x20000;
+ break;
+ default:
+ mmio_lower_reserved = 0x4000;
+ break;
+ }
+
range->fwnode = &of_root->fwnode;
- range->size = MMIO_LOWER_RESERVED;
+ range->size = mmio_lower_reserved;
range->hw_start = LOONGSON_PCIIO_BASE;
range->flags = LOGIC_PIO_CPU_MMIO;
@@ -89,9 +100,8 @@ static __init void reserve_pio_range(void)
* i8259 would access I/O space, so mapping must be done here.
* Please remove it when all drivers can be managed by logic_pio.
*/
- ioremap_page_range(PCI_IOBASE, PCI_IOBASE + MMIO_LOWER_RESERVED,
- LOONGSON_PCIIO_BASE,
- pgprot_device(PAGE_KERNEL));
+ ioremap_page_range(PCI_IOBASE, PCI_IOBASE + mmio_lower_reserved,
+ LOONGSON_PCIIO_BASE, pgprot_device(PAGE_KERNEL));
return;
unregister:
--
2.7.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/4] MIPS: Loongson64: Fix machine naming
2020-07-09 11:33 [PATCH 1/4] MIPS: Loongson64: Fix machine naming Huacai Chen
` (2 preceding siblings ...)
2020-07-09 11:33 ` [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type Huacai Chen
@ 2020-07-14 7:25 ` Tiezhu Yang
2020-07-16 10:00 ` Thomas Bogendoerfer
4 siblings, 0 replies; 15+ messages in thread
From: Tiezhu Yang @ 2020-07-14 7:25 UTC (permalink / raw)
To: Huacai Chen, Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On 07/09/2020 07:33 PM, Huacai Chen wrote:
> From previous commits, the machine names with "loongson3-" prefix have
> renamed to "loongson64c-" prefix in documents, but the .dts files have
> not been updated as well. So fix it.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts | 2 +-
> arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
> index acd53a1..d681a29 100644
> --- a/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
> +++ b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
> @@ -6,7 +6,7 @@
> #include "rs780e-pch.dtsi"
>
> / {
> - compatible = "loongson,loongson3-4core-rs780e";
> + compatible = "loongson,loongson64c-4core-rs780e";
> };
>
> &package0 {
> diff --git a/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
> index 433f9c3..3c20441 100644
> --- a/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
> +++ b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts
> @@ -6,7 +6,7 @@
> #include "rs780e-pch.dtsi"
>
> / {
> - compatible = "loongson,loongson3-8core-rs780e";
> + compatible = "loongson,loongson64c-8core-rs780e";
> };
>
> &package0 {
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH
2020-07-09 11:33 ` [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH Huacai Chen
@ 2020-07-14 7:26 ` Tiezhu Yang
2020-07-16 10:01 ` Thomas Bogendoerfer
1 sibling, 0 replies; 15+ messages in thread
From: Tiezhu Yang @ 2020-07-14 7:26 UTC (permalink / raw)
To: Huacai Chen, Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On 07/09/2020 07:33 PM, Huacai Chen wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and
> Generic Loongson64 Quad Core + LS7A boards.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/boot/dts/loongson/Makefile | 5 +-
> .../boot/dts/loongson/loongson64c_4core_ls7a.dts | 37 ++
> .../boot/dts/loongson/loongson64g-package.dtsi | 61 ++++
> .../boot/dts/loongson/loongson64g_4core_ls7a.dts | 37 ++
> arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 371 +++++++++++++++++++++
> .../include/asm/mach-loongson64/builtin_dtbs.h | 2 +
> 6 files changed, 512 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
> create mode 100644 arch/mips/boot/dts/loongson/loongson64g-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
>
> diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
> index aa5069a..ae1c8bf 100644
> --- a/arch/mips/boot/dts/loongson/Makefile
> +++ b/arch/mips/boot/dts/loongson/Makefile
> @@ -1,4 +1,7 @@
> # SPDX_License_Identifier: GPL_2.0
> -dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb loongson64c_8core_rs780e.dtb
> +dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb
> +dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
> +dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
> +dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
>
> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
> new file mode 100644
> index 00000000..c7ea4f1c
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "loongson64c-package.dtsi"
> +#include "ls7a-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,loongson64c-4core-ls7a";
> +};
> +
> +&package0 {
> + htvec: interrupt-controller@efdfb000080 {
> + compatible = "loongson,htvec-1.0";
> + reg = <0xefd 0xfb000080 0x40>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&liointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +};
> +
> +&pch {
> + msi: msi-controller@2ff00000 {
> + compatible = "loongson,pch-msi-1.0";
> + reg = <0 0x2ff00000 0 0x8>;
> + interrupt-controller;
> + msi-controller;
> + loongson,msi-base-vec = <64>;
> + loongson,msi-num-vecs = <64>;
> + interrupt-parent = <&htvec>;
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/loongson64g-package.dtsi b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi
> new file mode 100644
> index 00000000..38abc57
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/loongson64g-package.dtsi
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + package0: bus@1fe00000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
> + 0 0x3ff00000 0 0x3ff00000 0x100000
> + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
> +
> + liointc: interrupt-controller@3ff01400 {
> + compatible = "loongson,liointc-1.0";
> + reg = <0 0x3ff01400 0x64>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>, <3>;
> + interrupt-names = "int0", "int1";
> +
> + loongson,parent_int_map = <0x00ffffff>, /* int0 */
> + <0xff000000>, /* int1 */
> + <0x00000000>, /* int2 */
> + <0x00000000>; /* int3 */
> +
> + };
> +
> + cpu_uart0: serial@1fe001e0 {
> + compatible = "ns16550a";
> + reg = <0 0x1fe00100 0x10>;
> + clock-frequency = <100000000>;
> + interrupt-parent = <&liointc>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + no-loopback-test;
> + };
> +
> + cpu_uart1: serial@1fe001e8 {
> + status = "disabled";
> + compatible = "ns16550a";
> + reg = <0 0x1fe00110 0x10>;
> + clock-frequency = <100000000>;
> + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&liointc>;
> + no-loopback-test;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
> new file mode 100644
> index 00000000..bdc911e
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include "loongson64g-package.dtsi"
> +#include "ls7a-pch.dtsi"
> +
> +/ {
> + compatible = "loongson,loongson64g-4core-ls7a";
> +};
> +
> +&package0 {
> + htvec: interrupt-controller@efdfb000080 {
> + compatible = "loongson,htvec-1.0";
> + reg = <0xefd 0xfb000080 0x40>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&liointc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
> + <25 IRQ_TYPE_LEVEL_HIGH>,
> + <26 IRQ_TYPE_LEVEL_HIGH>,
> + <27 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +};
> +
> +&pch {
> + msi: msi-controller@2ff00000 {
> + compatible = "loongson,pch-msi-1.0";
> + reg = <0 0x2ff00000 0 0x8>;
> + interrupt-controller;
> + msi-controller;
> + loongson,msi-base-vec = <64>;
> + loongson,msi-num-vecs = <128>;
> + interrupt-parent = <&htvec>;
> + };
> +};
> diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> new file mode 100644
> index 00000000..1c286bb
> --- /dev/null
> +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
> @@ -0,0 +1,371 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/ {
> + pch: bus@10000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
> + 0 0x20000000 0 0x20000000 0 0x10000000
> + 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
> + 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
> +
> + pic: interrupt-controller@10000000 {
> + compatible = "loongson,pch-pic-1.0";
> + reg = <0 0x10000000 0 0x400>;
> + interrupt-controller;
> + interrupt-parent = <&htvec>;
> + loongson,pic-base-vec = <0>;
> + #interrupt-cells = <2>;
> + };
> +
> + pci@1a000000 {
> + compatible = "loongson,ls7a-pci";
> + device_type = "pci";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <2>;
> + msi-parent = <&msi>;
> +
> + reg = <0 0x1a000000 0 0x02000000>,
> + <0xefe 0x00000000 0 0x20000000>;
> +
> + ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
> + <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
> +
> + ohci@4,0 {
> + compatible = "pci0014,7a24.0",
> + "pci0014,7a24",
> + "pciclass0c0310",
> + "pciclass0c03";
> +
> + reg = <0x2000 0x0 0x0 0x0 0x0>;
> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + ehci@4,1 {
> + compatible = "pci0014,7a14.0",
> + "pci0014,7a14",
> + "pciclass0c0320",
> + "pciclass0c03";
> +
> + reg = <0x2100 0x0 0x0 0x0 0x0>;
> + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + ohci@5,0 {
> + compatible = "pci0014,7a24.0",
> + "pci0014,7a24",
> + "pciclass0c0310",
> + "pciclass0c03";
> +
> + reg = <0x2800 0x0 0x0 0x0 0x0>;
> + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + ehci@5,1 {
> + compatible = "pci0014,7a14.0",
> + "pci0014,7a14",
> + "pciclass0c0320",
> + "pciclass0c03";
> +
> + reg = <0x2900 0x0 0x0 0x0 0x0>;
> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + sata@8,0 {
> + compatible = "pci0014,7a08.0",
> + "pci0014,7a08",
> + "pciclass010601",
> + "pciclass0106";
> +
> + reg = <0x4000 0x0 0x0 0x0 0x0>;
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + sata@8,1 {
> + compatible = "pci0014,7a08.0",
> + "pci0014,7a08",
> + "pciclass010601",
> + "pciclass0106";
> +
> + reg = <0x4100 0x0 0x0 0x0 0x0>;
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + sata@8,2 {
> + compatible = "pci0014,7a08.0",
> + "pci0014,7a08",
> + "pciclass010601",
> + "pciclass0106";
> +
> + reg = <0x4200 0x0 0x0 0x0 0x0>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + gpu@6,0 {
> + compatible = "pci0014,7a15.0",
> + "pci0014,7a15",
> + "pciclass030200",
> + "pciclass0302";
> +
> + reg = <0x3000 0x0 0x0 0x0 0x0>;
> + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + dc@6,1 {
> + compatible = "pci0014,7a06.0",
> + "pci0014,7a06",
> + "pciclass030000",
> + "pciclass0300";
> +
> + reg = <0x3100 0x0 0x0 0x0 0x0>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + hda@7,0 {
> + compatible = "pci0014,7a07.0",
> + "pci0014,7a07",
> + "pciclass040300",
> + "pciclass0403";
> +
> + reg = <0x3800 0x0 0x0 0x0 0x0>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> + };
> +
> + gmac@3,0 {
> + compatible = "pci0014,7a03.0",
> + "pci0014,7a03",
> + "pciclass020000",
> + "pciclass0200";
> +
> + reg = <0x1800 0x0 0x0 0x0 0x0>;
> + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
> + <13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_lpi";
> + interrupt-parent = <&pic>;
> + phy-mode = "rgmii";
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> + };
> + };
> +
> + gmac@3,1 {
> + compatible = "pci0014,7a03.0",
> + "pci0014,7a03",
> + "pciclass020000",
> + "pciclass0200";
> +
> + reg = <0x1900 0x0 0x0 0x0 0x0>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
> + <15 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_lpi";
> + interrupt-parent = <&pic>;
> + phy-mode = "rgmii";
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> + phy1: ethernet-phy@1 {
> + reg = <0>;
> + };
> + };
> + };
> +
> + pci_bridge@9,0 {
> + compatible = "pci0014,7a19.1",
> + "pci0014,7a19",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x4800 0x0 0x0 0x0 0x0>;
> + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@a,0 {
> + compatible = "pci0014,7a09.1",
> + "pci0014,7a09",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x5000 0x0 0x0 0x0 0x0>;
> + interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@b,0 {
> + compatible = "pci0014,7a09.1",
> + "pci0014,7a09",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x5800 0x0 0x0 0x0 0x0>;
> + interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@c,0 {
> + compatible = "pci0014,7a09.1",
> + "pci0014,7a09",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x6000 0x0 0x0 0x0 0x0>;
> + interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@d,0 {
> + compatible = "pci0014,7a19.1",
> + "pci0014,7a19",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x6800 0x0 0x0 0x0 0x0>;
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@e,0 {
> + compatible = "pci0014,7a09.1",
> + "pci0014,7a09",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x7000 0x0 0x0 0x0 0x0>;
> + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@f,0 {
> + compatible = "pci0014,7a29.1",
> + "pci0014,7a29",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x7800 0x0 0x0 0x0 0x0>;
> + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@10,0 {
> + compatible = "pci0014,7a19.1",
> + "pci0014,7a19",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x8000 0x0 0x0 0x0 0x0>;
> + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@11,0 {
> + compatible = "pci0014,7a29.1",
> + "pci0014,7a29",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x8800 0x0 0x0 0x0 0x0>;
> + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@12,0 {
> + compatible = "pci0014,7a19.1",
> + "pci0014,7a19",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x9000 0x0 0x0 0x0 0x0>;
> + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@13,0 {
> + compatible = "pci0014,7a29.1",
> + "pci0014,7a29",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0x9800 0x0 0x0 0x0 0x0>;
> + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pci_bridge@14,0 {
> + compatible = "pci0014,7a19.1",
> + "pci0014,7a19",
> + "pciclass060400",
> + "pciclass0604";
> +
> + reg = <0xa000 0x0 0x0 0x0 0x0>;
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pic>;
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +};
> diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
> index 930c8a1..6d2f141 100644
> --- a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
> +++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
> @@ -8,6 +8,8 @@
> #ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
> #define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
>
> +extern u32 __dtb_loongson64c_4core_ls7a_begin[];
> extern u32 __dtb_loongson64c_4core_rs780e_begin[];
> extern u32 __dtb_loongson64c_8core_rs780e_begin[];
> +extern u32 __dtb_loongson64g_4core_ls7a_begin[];
> #endif
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs
2020-07-09 11:33 ` [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs Huacai Chen
@ 2020-07-14 7:27 ` Tiezhu Yang
2020-07-16 10:01 ` Thomas Bogendoerfer
1 sibling, 0 replies; 15+ messages in thread
From: Tiezhu Yang @ 2020-07-14 7:27 UTC (permalink / raw)
To: Huacai Chen, Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On 07/09/2020 07:33 PM, Huacai Chen wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> Load correct devicetree according to PRID and PCH type.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/loongson64/env.c | 56 ++++++++++++++++++++++++++++------------------
> 1 file changed, 34 insertions(+), 22 deletions(-)
>
> diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
> index 3e7caba..2cb9573 100644
> --- a/arch/mips/loongson64/env.c
> +++ b/arch/mips/loongson64/env.c
> @@ -126,28 +126,6 @@ void __init prom_init_env(void)
> loongson_sysconf.cores_per_node - 1) /
> loongson_sysconf.cores_per_node;
>
> - if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
> - switch (read_c0_prid() & PRID_REV_MASK) {
> - case PRID_REV_LOONGSON3A_R1:
> - case PRID_REV_LOONGSON3A_R2_0:
> - case PRID_REV_LOONGSON3A_R2_1:
> - case PRID_REV_LOONGSON3A_R3_0:
> - case PRID_REV_LOONGSON3A_R3_1:
> - loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
> - break;
> - case PRID_REV_LOONGSON3B_R1:
> - case PRID_REV_LOONGSON3B_R2:
> - loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
> - break;
> - default:
> - break;
> - }
> - }
> -
> -
> - if (!loongson_fdt_blob)
> - pr_err("Failed to determine built-in Loongson64 dtb\n");
> -
> loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
> loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
> loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
> @@ -198,4 +176,38 @@ void __init prom_init_env(void)
> loongson_sysconf.bridgetype = RS780E;
> loongson_sysconf.early_config = rs780e_early_config;
> }
> +
> + if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
> + switch (read_c0_prid() & PRID_REV_MASK) {
> + case PRID_REV_LOONGSON3A_R1:
> + case PRID_REV_LOONGSON3A_R2_0:
> + case PRID_REV_LOONGSON3A_R2_1:
> + case PRID_REV_LOONGSON3A_R3_0:
> + case PRID_REV_LOONGSON3A_R3_1:
> + switch (loongson_sysconf.bridgetype) {
> + case LS7A:
> + loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
> + break;
> + case RS780E:
> + loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
> + break;
> + default:
> + break;
> + }
> + break;
> + case PRID_REV_LOONGSON3B_R1:
> + case PRID_REV_LOONGSON3B_R2:
> + if (loongson_sysconf.bridgetype == RS780E)
> + loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
> + break;
> + default:
> + break;
> + }
> + } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
> + if (loongson_sysconf.bridgetype == LS7A)
> + loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
> + }
> +
> + if (!loongson_fdt_blob)
> + pr_err("Failed to determine built-in Loongson64 dtb\n");
> }
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type
2020-07-09 11:33 ` [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type Huacai Chen
@ 2020-07-14 7:27 ` Tiezhu Yang
2020-07-16 10:00 ` Thomas Bogendoerfer
1 sibling, 0 replies; 15+ messages in thread
From: Tiezhu Yang @ 2020-07-14 7:27 UTC (permalink / raw)
To: Huacai Chen, Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On 07/09/2020 07:33 PM, Huacai Chen wrote:
> Define MMIO_LOWER_RESERVED as a constant is incorrect, because different
> PCHs (bridge types) have different legacy MMIO space size. According to
> the datasheets, the legacy MMIO space size of LS7A is 0x20000, and which
> of other PCHs is 0x4000. So it is necessary to reserve legacy MMIO space
> according to the bridge type.
>
> Currently IO_SPACE_LIMIT is defined as 0xffff which is too small for the
> LS7A bridge, so increase it to 0xfffff for LOONGSON64.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
> arch/mips/include/asm/io.h | 4 ++++
> arch/mips/include/asm/mach-loongson64/spaces.h | 3 ---
> arch/mips/loongson64/init.c | 18 ++++++++++++++----
> 3 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 346fffd..7358372 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -51,7 +51,11 @@
>
> /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
>
> +#ifndef CONFIG_CPU_LOONGSON64
> #define IO_SPACE_LIMIT 0xffff
> +#else
> +#define IO_SPACE_LIMIT 0xfffff
> +#endif
>
> /*
> * On MIPS I/O ports are memory mapped, so we access them using normal
> diff --git a/arch/mips/include/asm/mach-loongson64/spaces.h b/arch/mips/include/asm/mach-loongson64/spaces.h
> index 3de0ac9..93bdd9e 100644
> --- a/arch/mips/include/asm/mach-loongson64/spaces.h
> +++ b/arch/mips/include/asm/mach-loongson64/spaces.h
> @@ -11,8 +11,5 @@
> #define PCI_IOSIZE SZ_16M
> #define MAP_BASE (PCI_IOBASE + PCI_IOSIZE)
>
> -/* Reserved at the start of PCI_IOBASE for legacy drivers */
> -#define MMIO_LOWER_RESERVED 0x10000
> -
> #include <asm/mach-generic/spaces.h>
> #endif
> diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
> index 59ddada..606cdc4 100644
> --- a/arch/mips/loongson64/init.c
> +++ b/arch/mips/loongson64/init.c
> @@ -65,14 +65,25 @@ void __init prom_free_prom_memory(void)
>
> static __init void reserve_pio_range(void)
> {
> + /* Reserved at the start of PCI_IOBASE for legacy drivers */
> + int mmio_lower_reserved;
> struct logic_pio_hwaddr *range;
>
> range = kzalloc(sizeof(*range), GFP_ATOMIC);
> if (!range)
> return;
>
> + switch (loongson_sysconf.bridgetype) {
> + case LS7A:
> + mmio_lower_reserved = 0x20000;
> + break;
> + default:
> + mmio_lower_reserved = 0x4000;
> + break;
> + }
> +
> range->fwnode = &of_root->fwnode;
> - range->size = MMIO_LOWER_RESERVED;
> + range->size = mmio_lower_reserved;
> range->hw_start = LOONGSON_PCIIO_BASE;
> range->flags = LOGIC_PIO_CPU_MMIO;
>
> @@ -89,9 +100,8 @@ static __init void reserve_pio_range(void)
> * i8259 would access I/O space, so mapping must be done here.
> * Please remove it when all drivers can be managed by logic_pio.
> */
> - ioremap_page_range(PCI_IOBASE, PCI_IOBASE + MMIO_LOWER_RESERVED,
> - LOONGSON_PCIIO_BASE,
> - pgprot_device(PAGE_KERNEL));
> + ioremap_page_range(PCI_IOBASE, PCI_IOBASE + mmio_lower_reserved,
> + LOONGSON_PCIIO_BASE, pgprot_device(PAGE_KERNEL));
>
> return;
> unregister:
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type
2020-07-09 11:33 ` [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type Huacai Chen
2020-07-14 7:27 ` Tiezhu Yang
@ 2020-07-16 10:00 ` Thomas Bogendoerfer
2020-07-16 11:10 ` Huacai Chen
1 sibling, 1 reply; 15+ messages in thread
From: Thomas Bogendoerfer @ 2020-07-16 10:00 UTC (permalink / raw)
To: Huacai Chen
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On Thu, Jul 09, 2020 at 07:33:44PM +0800, Huacai Chen wrote:
> Define MMIO_LOWER_RESERVED as a constant is incorrect, because different
> PCHs (bridge types) have different legacy MMIO space size. According to
> the datasheets, the legacy MMIO space size of LS7A is 0x20000, and which
> of other PCHs is 0x4000. So it is necessary to reserve legacy MMIO space
> according to the bridge type.
>
> Currently IO_SPACE_LIMIT is defined as 0xffff which is too small for the
> LS7A bridge, so increase it to 0xfffff for LOONGSON64.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> arch/mips/include/asm/io.h | 4 ++++
> arch/mips/include/asm/mach-loongson64/spaces.h | 3 ---
> arch/mips/loongson64/init.c | 18 ++++++++++++++----
> 3 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 346fffd..7358372 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -51,7 +51,11 @@
>
> /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
>
> +#ifndef CONFIG_CPU_LOONGSON64
> #define IO_SPACE_LIMIT 0xffff
> +#else
> +#define IO_SPACE_LIMIT 0xfffff
> +#endif
can you please move this #define to mach-generic/spaces.h and
override it in mach-loongson64/spaces.h ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/4] MIPS: Loongson64: Fix machine naming
2020-07-09 11:33 [PATCH 1/4] MIPS: Loongson64: Fix machine naming Huacai Chen
` (3 preceding siblings ...)
2020-07-14 7:25 ` [PATCH 1/4] MIPS: Loongson64: Fix machine naming Tiezhu Yang
@ 2020-07-16 10:00 ` Thomas Bogendoerfer
4 siblings, 0 replies; 15+ messages in thread
From: Thomas Bogendoerfer @ 2020-07-16 10:00 UTC (permalink / raw)
To: Huacai Chen
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On Thu, Jul 09, 2020 at 07:33:41PM +0800, Huacai Chen wrote:
> >From previous commits, the machine names with "loongson3-" prefix have
> renamed to "loongson64c-" prefix in documents, but the .dts files have
> not been updated as well. So fix it.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts | 2 +-
> arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH
2020-07-09 11:33 ` [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH Huacai Chen
2020-07-14 7:26 ` Tiezhu Yang
@ 2020-07-16 10:01 ` Thomas Bogendoerfer
1 sibling, 0 replies; 15+ messages in thread
From: Thomas Bogendoerfer @ 2020-07-16 10:01 UTC (permalink / raw)
To: Huacai Chen
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On Thu, Jul 09, 2020 at 07:33:42PM +0800, Huacai Chen wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and
> Generic Loongson64 Quad Core + LS7A boards.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> arch/mips/boot/dts/loongson/Makefile | 5 +-
> .../boot/dts/loongson/loongson64c_4core_ls7a.dts | 37 ++
> .../boot/dts/loongson/loongson64g-package.dtsi | 61 ++++
> .../boot/dts/loongson/loongson64g_4core_ls7a.dts | 37 ++
> arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 371 +++++++++++++++++++++
> .../include/asm/mach-loongson64/builtin_dtbs.h | 2 +
> 6 files changed, 512 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
> create mode 100644 arch/mips/boot/dts/loongson/loongson64g-package.dtsi
> create mode 100644 arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
> create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs
2020-07-09 11:33 ` [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs Huacai Chen
2020-07-14 7:27 ` Tiezhu Yang
@ 2020-07-16 10:01 ` Thomas Bogendoerfer
1 sibling, 0 replies; 15+ messages in thread
From: Thomas Bogendoerfer @ 2020-07-16 10:01 UTC (permalink / raw)
To: Huacai Chen
Cc: linux-mips, Fuxin Zhang, Zhangjin Wu, Huacai Chen, Jiaxun Yang
On Thu, Jul 09, 2020 at 07:33:43PM +0800, Huacai Chen wrote:
> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> Load correct devicetree according to PRID and PCH type.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> arch/mips/loongson64/env.c | 56 ++++++++++++++++++++++++++++------------------
> 1 file changed, 34 insertions(+), 22 deletions(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type
2020-07-16 10:00 ` Thomas Bogendoerfer
@ 2020-07-16 11:10 ` Huacai Chen
2020-07-16 12:04 ` Thomas Bogendoerfer
0 siblings, 1 reply; 15+ messages in thread
From: Huacai Chen @ 2020-07-16 11:10 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: open list:MIPS, Fuxin Zhang, Zhangjin Wu, Jiaxun Yang
Hi, Thomas,
On Thu, Jul 16, 2020 at 6:01 PM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Thu, Jul 09, 2020 at 07:33:44PM +0800, Huacai Chen wrote:
> > Define MMIO_LOWER_RESERVED as a constant is incorrect, because different
> > PCHs (bridge types) have different legacy MMIO space size. According to
> > the datasheets, the legacy MMIO space size of LS7A is 0x20000, and which
> > of other PCHs is 0x4000. So it is necessary to reserve legacy MMIO space
> > according to the bridge type.
> >
> > Currently IO_SPACE_LIMIT is defined as 0xffff which is too small for the
> > LS7A bridge, so increase it to 0xfffff for LOONGSON64.
> >
> > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > ---
> > arch/mips/include/asm/io.h | 4 ++++
> > arch/mips/include/asm/mach-loongson64/spaces.h | 3 ---
> > arch/mips/loongson64/init.c | 18 ++++++++++++++----
> > 3 files changed, 18 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> > index 346fffd..7358372 100644
> > --- a/arch/mips/include/asm/io.h
> > +++ b/arch/mips/include/asm/io.h
> > @@ -51,7 +51,11 @@
> >
> > /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
> >
> > +#ifndef CONFIG_CPU_LOONGSON64
> > #define IO_SPACE_LIMIT 0xffff
> > +#else
> > +#define IO_SPACE_LIMIT 0xfffff
> > +#endif
>
> can you please move this #define to mach-generic/spaces.h and
> override it in mach-loongson64/spaces.h ?
Maybe that's not a good idea, because all other archs define
IO_SPACE_LIMIT in io.h, moving to another file may cause some build
errors.
Huacai
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type
2020-07-16 11:10 ` Huacai Chen
@ 2020-07-16 12:04 ` Thomas Bogendoerfer
2020-07-17 1:33 ` Huacai Chen
0 siblings, 1 reply; 15+ messages in thread
From: Thomas Bogendoerfer @ 2020-07-16 12:04 UTC (permalink / raw)
To: Huacai Chen; +Cc: open list:MIPS, Fuxin Zhang, Zhangjin Wu, Jiaxun Yang
On Thu, Jul 16, 2020 at 07:10:09PM +0800, Huacai Chen wrote:
> Hi, Thomas,
>
> On Thu, Jul 16, 2020 at 6:01 PM Thomas Bogendoerfer
> <tsbogend@alpha.franken.de> wrote:
> >
> > On Thu, Jul 09, 2020 at 07:33:44PM +0800, Huacai Chen wrote:
> > > Define MMIO_LOWER_RESERVED as a constant is incorrect, because different
> > > PCHs (bridge types) have different legacy MMIO space size. According to
> > > the datasheets, the legacy MMIO space size of LS7A is 0x20000, and which
> > > of other PCHs is 0x4000. So it is necessary to reserve legacy MMIO space
> > > according to the bridge type.
> > >
> > > Currently IO_SPACE_LIMIT is defined as 0xffff which is too small for the
> > > LS7A bridge, so increase it to 0xfffff for LOONGSON64.
> > >
> > > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > > ---
> > > arch/mips/include/asm/io.h | 4 ++++
> > > arch/mips/include/asm/mach-loongson64/spaces.h | 3 ---
> > > arch/mips/loongson64/init.c | 18 ++++++++++++++----
> > > 3 files changed, 18 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> > > index 346fffd..7358372 100644
> > > --- a/arch/mips/include/asm/io.h
> > > +++ b/arch/mips/include/asm/io.h
> > > @@ -51,7 +51,11 @@
> > >
> > > /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
> > >
> > > +#ifndef CONFIG_CPU_LOONGSON64
> > > #define IO_SPACE_LIMIT 0xffff
> > > +#else
> > > +#define IO_SPACE_LIMIT 0xfffff
> > > +#endif
> >
> > can you please move this #define to mach-generic/spaces.h and
> > override it in mach-loongson64/spaces.h ?
> Maybe that's not a good idea, because all other archs define
> IO_SPACE_LIMIT in io.h, moving to another file may cause some build
> errors.
it's already included via asm/addrspace.h
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type
2020-07-16 12:04 ` Thomas Bogendoerfer
@ 2020-07-17 1:33 ` Huacai Chen
0 siblings, 0 replies; 15+ messages in thread
From: Huacai Chen @ 2020-07-17 1:33 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: open list:MIPS, Fuxin Zhang, Zhangjin Wu, Jiaxun Yang
Hi, Thomas,
On Thu, Jul 16, 2020 at 8:05 PM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
>
> On Thu, Jul 16, 2020 at 07:10:09PM +0800, Huacai Chen wrote:
> > Hi, Thomas,
> >
> > On Thu, Jul 16, 2020 at 6:01 PM Thomas Bogendoerfer
> > <tsbogend@alpha.franken.de> wrote:
> > >
> > > On Thu, Jul 09, 2020 at 07:33:44PM +0800, Huacai Chen wrote:
> > > > Define MMIO_LOWER_RESERVED as a constant is incorrect, because different
> > > > PCHs (bridge types) have different legacy MMIO space size. According to
> > > > the datasheets, the legacy MMIO space size of LS7A is 0x20000, and which
> > > > of other PCHs is 0x4000. So it is necessary to reserve legacy MMIO space
> > > > according to the bridge type.
> > > >
> > > > Currently IO_SPACE_LIMIT is defined as 0xffff which is too small for the
> > > > LS7A bridge, so increase it to 0xfffff for LOONGSON64.
> > > >
> > > > Signed-off-by: Huacai Chen <chenhc@lemote.com>
> > > > ---
> > > > arch/mips/include/asm/io.h | 4 ++++
> > > > arch/mips/include/asm/mach-loongson64/spaces.h | 3 ---
> > > > arch/mips/loongson64/init.c | 18 ++++++++++++++----
> > > > 3 files changed, 18 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> > > > index 346fffd..7358372 100644
> > > > --- a/arch/mips/include/asm/io.h
> > > > +++ b/arch/mips/include/asm/io.h
> > > > @@ -51,7 +51,11 @@
> > > >
> > > > /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
> > > >
> > > > +#ifndef CONFIG_CPU_LOONGSON64
> > > > #define IO_SPACE_LIMIT 0xffff
> > > > +#else
> > > > +#define IO_SPACE_LIMIT 0xfffff
> > > > +#endif
> > >
> > > can you please move this #define to mach-generic/spaces.h and
> > > override it in mach-loongson64/spaces.h ?
> > Maybe that's not a good idea, because all other archs define
> > IO_SPACE_LIMIT in io.h, moving to another file may cause some build
> > errors.
>
> it's already included via asm/addrspace.h
Yes, you are right, I'll send V2.
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-07-17 1:33 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-09 11:33 [PATCH 1/4] MIPS: Loongson64: Fix machine naming Huacai Chen
2020-07-09 11:33 ` [PATCH 2/4] MIPS: Loongson64: DeviceTree for LS7A PCH Huacai Chen
2020-07-14 7:26 ` Tiezhu Yang
2020-07-16 10:01 ` Thomas Bogendoerfer
2020-07-09 11:33 ` [PATCH 3/4] MIPS: Loongson64: Load LS7A dtbs Huacai Chen
2020-07-14 7:27 ` Tiezhu Yang
2020-07-16 10:01 ` Thomas Bogendoerfer
2020-07-09 11:33 ` [PATCH 4/4] MIPS: Loongson64: Reserve legacy MMIO space according to bridge type Huacai Chen
2020-07-14 7:27 ` Tiezhu Yang
2020-07-16 10:00 ` Thomas Bogendoerfer
2020-07-16 11:10 ` Huacai Chen
2020-07-16 12:04 ` Thomas Bogendoerfer
2020-07-17 1:33 ` Huacai Chen
2020-07-14 7:25 ` [PATCH 1/4] MIPS: Loongson64: Fix machine naming Tiezhu Yang
2020-07-16 10:00 ` Thomas Bogendoerfer
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