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From: Huang Pei <huangpei@loongson.cn>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>, ambrosehua@gmail.com
Cc: Li Xuefeng <lixuefeng@loongson.cn>,
	Yang Tiezhu <yangtiezhu@loongson.cn>,
	Gao Juxin <gaojuxin@loongson.cn>,
	Fuxin Zhang <zhangfx@lemote.com>, Huacai Chen <chenhc@lemote.com>,
	linux-mips@vger.kernel.org
Subject: [PATCH 1/3] MIPS: add missing MSACSR and upper MSA initialization
Date: Fri, 21 Aug 2020 15:23:27 +0800	[thread overview]
Message-ID: <20200821072329.18006-1-huangpei@loongson.cn> (raw)

own_fp_inatomic() does not restore/initialize MSACSR and upper MSA regs, so
MSACSR and MSA upper regs's value from previous task on current cpu can leak
into current task and cause unpredictable behavior when MSA context not
initialized.

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/kernel/traps.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 38aa07ccdbcc..99a8f1b7b522 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1287,6 +1287,8 @@ static int enable_restore_fp_context(int msa)
 		err = own_fpu_inatomic(1);
 		if (msa && !err) {
 			enable_msa();
+			write_msa_csr(current->thread.fpu.msacsr);
+			init_msa_upper();
 			set_thread_flag(TIF_USEDMSA);
 			set_thread_flag(TIF_MSA_CTX_LIVE);
 		}
-- 
2.17.1


             reply	other threads:[~2020-08-21  7:23 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-21  7:23 Huang Pei [this message]
2020-08-21  7:23 ` [PATCH 2/3] MIPS: make userspace mapping young by default Huang Pei
2020-08-21  7:23 ` [PATCH 3/3] Revert "MIPS: Flush wrong invalid FTLB entry for huge page" Huang Pei
2020-08-21  9:26   ` Huacai Chen
2020-08-22  4:27     ` 答复： " 黄沛
2020-08-24  7:13       ` Huacai Chen
2020-08-24 10:19         ` Huang Pei
2020-08-24  7:19 ` [PATCH 1/3] MIPS: add missing MSACSR and upper MSA initialization Huacai Chen
2020-08-25  7:40   ` Huacai Chen

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