From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Heiher <r@hev.cc>
Cc: linux-mips@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhc@lemote.com>,
Paul Burton <paulburton@kernel.org>,
"Maciej W . Rozycki" <macro@linux-mips.org>
Subject: Re: [PATCH] MIPS: Optional SYNC emulation
Date: Wed, 30 Sep 2020 13:16:44 +0200 [thread overview]
Message-ID: <20200930111644.GA19903@alpha.franken.de> (raw)
In-Reply-To: <20200821031228.31231-1-r@hev.cc>
On Fri, Aug 21, 2020 at 11:12:28AM +0800, Heiher wrote:
> MIPS ISA defines several types of memory barrier, of which Type-0 (full barrier)
> is required, and the others are optional. In some vendor implementation (such as
> Loongson), all optional parts are implemented to emit an illegal instruction
> exception. Here, emulate to full barrier to ensure the functional semantics.
>
> If an implementation does not support SYNC 0, it should also not support SMP, so
> the `smp_mb()` is only a compilation barrier.
I see your point, but isn't taking an exception already more than a
compiler barrier ? Does the missing sync hurt in real life ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2020-09-30 12:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-21 3:12 [PATCH] MIPS: Optional SYNC emulation Heiher
2020-09-30 11:16 ` Thomas Bogendoerfer [this message]
2020-10-01 7:45 ` Hev
2020-11-02 12:33 ` Maciej W. Rozycki
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