From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
linux-mips@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Lars Povlsen <lars.povlsen@microchip.com>,
<Steen.Hegelund@microchip.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>
Subject: [PATCH 5/9] MIPS: mscc: Add luton dtsi
Date: Fri, 6 Nov 2020 11:08:45 +0100 [thread overview]
Message-ID: <20201106100849.969240-7-gregory.clement@bootlin.com> (raw)
In-Reply-To: <20201106100849.969240-1-gregory.clement@bootlin.com>
Add a device tree include file for the Microsemi Luton SoC which
belongs to same family of the Ocelot SoC.
It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/dts/mscc/luton.dtsi | 116 +++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
create mode 100644 arch/mips/boot/dts/mscc/luton.dtsi
diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi
new file mode 100644
index 000000000000..2a170b84c5a9
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/luton.dtsi
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microsemi Corporation */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb@60000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x60000000 0x20000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@10000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x10000000 0x2c>;
+ };
+
+ intc: interrupt-controller@10000084 {
+ compatible = "mscc,luton-icpu-intr";
+ reg = <0x10000084 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ i2c0: i2c@10100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x10100400 0x100>, <0x100002a4 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <11>;
+ clocks = <&ahb_clk>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x28>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 32>;
+ interrupt-controller;
+ interrupts = <13>;
+ #interrupt-cells = <2>;
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_5", "GPIO_6";
+ function = "twi";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+ };
+};
--
2.28.0
next prev parent reply other threads:[~2020-11-06 10:13 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add luton Gregory CLEMENT
2020-11-06 13:04 ` Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add Luton Gregory CLEMENT
2020-11-09 21:38 ` Rob Herring
2020-11-06 10:08 ` [PATCH 2/9] dt-bindings: mips: Add Serval and Jaguar2 Gregory CLEMENT
2020-11-09 21:38 ` Rob Herring
2020-11-06 10:08 ` [PATCH 3/9] MIPS: mscc: Prepare configuration to handle more SoCs Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 4/9] MIPS: mscc: Fix configuration name for ocelot legacy boards Gregory CLEMENT
2020-11-06 10:08 ` Gregory CLEMENT [this message]
2020-11-06 10:08 ` [PATCH 6/9] MIPS: mscc: Add luton PC0B91 device tree Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 7/9] MIPS: mscc: build FIT image for Luton Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 8/9] MIPS: mscc: Add jaguar2 support Gregory CLEMENT
2020-11-09 16:36 ` Gregory CLEMENT
2020-11-09 21:42 ` Rob Herring
2020-11-06 10:08 ` [PATCH 9/9] MIPS: mscc: Add serval support Gregory CLEMENT
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