* [PATCH 1/9] dt-bindings: mips: Add luton
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-06 13:04 ` Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add Luton Gregory CLEMENT
` (8 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Luton SoCs belongs to the same family as Ocelot.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/mips/mscc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
index bc817e984628..cc93fd302553 100644
--- a/Documentation/devicetree/bindings/mips/mscc.txt
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
-- compatible: "mscc,ocelot"
+- compatible: "mscc,ocelot" or "mscc,luton"
* Other peripherals:
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 1/9] dt-bindings: mips: Add luton
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add luton Gregory CLEMENT
@ 2020-11-06 13:04 ` Gregory CLEMENT
0 siblings, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 13:04 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund
Hello
This patch is a leftover, the correct one is the other one. Actually the
only difference is using "Luton" instead of "luton" in the topic.
Gregory
Gregory CLEMENT <gregory.clement@bootlin.com> writes:
> Luton SoCs belongs to the same family as Ocelot.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/mips/mscc.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
> index bc817e984628..cc93fd302553 100644
> --- a/Documentation/devicetree/bindings/mips/mscc.txt
> +++ b/Documentation/devicetree/bindings/mips/mscc.txt
> @@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
> properties:
>
> Required properties:
> -- compatible: "mscc,ocelot"
> +- compatible: "mscc,ocelot" or "mscc,luton"
>
>
> * Other peripherals:
> --
> 2.28.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/9] dt-bindings: mips: Add Luton
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add luton Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-09 21:38 ` Rob Herring
2020-11-06 10:08 ` [PATCH 2/9] dt-bindings: mips: Add Serval and Jaguar2 Gregory CLEMENT
` (7 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Luton SoC belongs to the same family as Ocelot.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/mips/mscc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
index bc817e984628..cc93fd302553 100644
--- a/Documentation/devicetree/bindings/mips/mscc.txt
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
-- compatible: "mscc,ocelot"
+- compatible: "mscc,ocelot" or "mscc,luton"
* Other peripherals:
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 1/9] dt-bindings: mips: Add Luton
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add Luton Gregory CLEMENT
@ 2020-11-09 21:38 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-11-09 21:38 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Steen.Hegelund, devicetree, Microchip Linux Driver Support,
Rob Herring, Alexandre Belloni, Thomas Petazzoni,
Thomas Bogendoerfer, linux-mips, Lars Povlsen
On Fri, 06 Nov 2020 11:08:41 +0100, Gregory CLEMENT wrote:
> Luton SoC belongs to the same family as Ocelot.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/mips/mscc.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/9] dt-bindings: mips: Add Serval and Jaguar2
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add luton Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 1/9] dt-bindings: mips: Add Luton Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-09 21:38 ` Rob Herring
2020-11-06 10:08 ` [PATCH 3/9] MIPS: mscc: Prepare configuration to handle more SoCs Gregory CLEMENT
` (6 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Serval and Jaguar2 SoCs belong to the same family as Ocelot and Luton.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/mips/mscc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
index cc93fd302553..bdbebb525393 100644
--- a/Documentation/devicetree/bindings/mips/mscc.txt
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
-- compatible: "mscc,ocelot" or "mscc,luton"
+- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jaguar2"
* Other peripherals:
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 2/9] dt-bindings: mips: Add Serval and Jaguar2
2020-11-06 10:08 ` [PATCH 2/9] dt-bindings: mips: Add Serval and Jaguar2 Gregory CLEMENT
@ 2020-11-09 21:38 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-11-09 21:38 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Steen.Hegelund, Rob Herring, Thomas Bogendoerfer,
Microchip Linux Driver Support, Lars Povlsen, devicetree,
linux-mips, Alexandre Belloni, Thomas Petazzoni
On Fri, 06 Nov 2020 11:08:42 +0100, Gregory CLEMENT wrote:
> Serval and Jaguar2 SoCs belong to the same family as Ocelot and Luton.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/mips/mscc.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/9] MIPS: mscc: Prepare configuration to handle more SoCs
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
` (2 preceding siblings ...)
2020-11-06 10:08 ` [PATCH 2/9] dt-bindings: mips: Add Serval and Jaguar2 Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 4/9] MIPS: mscc: Fix configuration name for ocelot legacy boards Gregory CLEMENT
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Ocelot belongs to a family of SoC named the VCore III. In order to add
these new Soc, use the new symbol SOC_VCOREIII instead of a one
dedicated to Ocelot.
In order to avoid regression on driver building, the MSCC_OCELOT
configuration symbol is kept until the driver will be converted.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/dts/Makefile | 2 +-
arch/mips/boot/dts/mscc/Makefile | 2 +-
arch/mips/generic/Kconfig | 11 ++++++++---
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 19027129add8..0259238d7a2e 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -6,7 +6,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
subdir-$(CONFIG_MACH_INGENIC) += ingenic
subdir-$(CONFIG_LANTIQ) += lantiq
subdir-$(CONFIG_MACH_LOONGSON64) += loongson
-subdir-$(CONFIG_MSCC_OCELOT) += mscc
+subdir-$(CONFIG_SOC_VCOREIII) += mscc
subdir-$(CONFIG_MIPS_MALTA) += mti
subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
subdir-$(CONFIG_NLM_XLP_BOARD) += netlogic
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index eb71515871f6..5015ccbbfb23 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb ocelot_pcb120.dtb
+dtb-$(CONFIG_SOC_VCOREIII) += ocelot_pcb123.dtb ocelot_pcb120.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 55d9aed7ced9..45431b88dded 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -34,14 +34,19 @@ config LEGACY_BOARD_OCELOT
bool "Support MSCC Ocelot boards"
depends on LEGACY_BOARD_SEAD3=n
select LEGACY_BOARDS
- select MSCC_OCELOT
+ select SOC_VCOREIII
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
-config MSCC_OCELOT
+config SOC_VCOREIII
bool
select GPIOLIB
select MSCC_OCELOT_IRQ
+ select MSCC_OCELOT #will be removed when driver no more use it
+
+#Will be removed when the driver using it will be converted to SOC_VCOREIII
+config MSCC_OCELOT
+ bool
comment "FIT/UHI Boards"
@@ -67,7 +72,7 @@ config FIT_IMAGE_FDT_XILFPGA
config FIT_IMAGE_FDT_OCELOT
bool "Include FDT for Microsemi Ocelot development platforms"
- select MSCC_OCELOT
+ select SOC_VCOREIII
help
Enable this to include the FDT for the Ocelot development platforms
from Microsemi in the FIT kernel image.
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/9] MIPS: mscc: Fix configuration name for ocelot legacy boards
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
` (3 preceding siblings ...)
2020-11-06 10:08 ` [PATCH 3/9] MIPS: mscc: Prepare configuration to handle more SoCs Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 5/9] MIPS: mscc: Add luton dtsi Gregory CLEMENT
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Ocelots is supported by the generic MIPS build so make it clears that
LEGACY_BOARD_OCELOT is only needed for legacy boards which didn't have
bootloader supporting device tree.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/generic/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 45431b88dded..eb2a3fa9fcd7 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -31,7 +31,7 @@ comment "MSCC Ocelot doesn't work with SEAD3 enabled"
depends on LEGACY_BOARD_SEAD3
config LEGACY_BOARD_OCELOT
- bool "Support MSCC Ocelot boards"
+ bool "Legacy support for Ocelot based boards"
depends on LEGACY_BOARD_SEAD3=n
select LEGACY_BOARDS
select SOC_VCOREIII
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 5/9] MIPS: mscc: Add luton dtsi
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
` (4 preceding siblings ...)
2020-11-06 10:08 ` [PATCH 4/9] MIPS: mscc: Fix configuration name for ocelot legacy boards Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 6/9] MIPS: mscc: Add luton PC0B91 device tree Gregory CLEMENT
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Add a device tree include file for the Microsemi Luton SoC which
belongs to same family of the Ocelot SoC.
It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/dts/mscc/luton.dtsi | 116 +++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
create mode 100644 arch/mips/boot/dts/mscc/luton.dtsi
diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi
new file mode 100644
index 000000000000..2a170b84c5a9
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/luton.dtsi
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microsemi Corporation */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb@60000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x60000000 0x20000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@10000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x10000000 0x2c>;
+ };
+
+ intc: interrupt-controller@10000084 {
+ compatible = "mscc,luton-icpu-intr";
+ reg = <0x10000084 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ i2c0: i2c@10100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x10100400 0x100>, <0x100002a4 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <11>;
+ clocks = <&ahb_clk>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x28>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 32>;
+ interrupt-controller;
+ interrupts = <13>;
+ #interrupt-cells = <2>;
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_5", "GPIO_6";
+ function = "twi";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+ };
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6/9] MIPS: mscc: Add luton PC0B91 device tree
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
` (5 preceding siblings ...)
2020-11-06 10:08 ` [PATCH 5/9] MIPS: mscc: Add luton dtsi Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 7/9] MIPS: mscc: build FIT image for Luton Gregory CLEMENT
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Add a device tree for the Microsemi Luton PCB091 evaluation board.
It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/dts/mscc/Makefile | 5 +++-
arch/mips/boot/dts/mscc/luton_pcb091.dts | 30 ++++++++++++++++++++++++
2 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/mscc/luton_pcb091.dts
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index 5015ccbbfb23..40699b44ed50 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -1,4 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_SOC_VCOREIII) += ocelot_pcb123.dtb ocelot_pcb120.dtb
+dtb-$(CONFIG_SOC_VCOREIII) += \
+ luton_pcb091.dtb \
+ ocelot_pcb120.dtb \
+ ocelot_pcb123.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/luton_pcb091.dts b/arch/mips/boot/dts/mscc/luton_pcb091.dts
new file mode 100644
index 000000000000..26ef6285d71d
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/luton_pcb091.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+/dts-v1/;
+
+#include "luton.dtsi"
+
+/ {
+ model = "Luton10 PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-sda-hold-time-ns = <300>;
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 7/9] MIPS: mscc: build FIT image for Luton
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
` (6 preceding siblings ...)
2020-11-06 10:08 ` [PATCH 6/9] MIPS: mscc: Add luton PC0B91 device tree Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 8/9] MIPS: mscc: Add jaguar2 support Gregory CLEMENT
2020-11-06 10:08 ` [PATCH 9/9] MIPS: mscc: Add serval support Gregory CLEMENT
9 siblings, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Luton now has already an u-boot port so let's build FIT images.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/generic/Kconfig | 8 ++++++++
arch/mips/generic/Platform | 1 +
arch/mips/generic/board-luton.its.S | 23 +++++++++++++++++++++++
3 files changed, 32 insertions(+)
create mode 100644 arch/mips/generic/board-luton.its.S
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index eb2a3fa9fcd7..e5a7a1314e71 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -78,6 +78,14 @@ config FIT_IMAGE_FDT_OCELOT
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
+config FIT_IMAGE_FDT_LUTON
+ bool "Include FDT for Microsemi Luton development platforms"
+ select SOC_VCOREIII
+ help
+ Enable this to include the FDT for the Luton development platforms
+ from Microsemi in the FIT kernel image.
+ This requires u-boot on the platform.
+
config BOARD_INGENIC
bool "Support boards based on Ingenic SoCs"
select MACH_INGENIC_GENERIC
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index f8ef2f9d107e..4b6905daa39c 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -20,4 +20,5 @@ its-y := vmlinux.its.S
its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
diff --git a/arch/mips/generic/board-luton.its.S b/arch/mips/generic/board-luton.its.S
new file mode 100644
index 000000000000..39a543f62f25
--- /dev/null
+++ b/arch/mips/generic/board-luton.its.S
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/ {
+ images {
+ fdt@luton_pcb091 {
+ description = "MSCC Luton PCB091 Device Tree";
+ data = /incbin/("boot/dts/mscc/luton_pcb091.dtb");
+ type = "flat_dt";
+ arch = "mips";
+ compression = "none";
+ hash@0 {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ pcb091 {
+ description = "Luton Linux kernel";
+ kernel = "kernel@0";
+ fdt = "fdt@luton_pcb091";
+ };
+ };
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 8/9] MIPS: mscc: Add jaguar2 support
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
` (7 preceding siblings ...)
2020-11-06 10:08 ` [PATCH 7/9] MIPS: mscc: build FIT image for Luton Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
2020-11-09 16:36 ` Gregory CLEMENT
2020-11-09 21:42 ` Rob Herring
2020-11-06 10:08 ` [PATCH 9/9] MIPS: mscc: Add serval support Gregory CLEMENT
9 siblings, 2 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Add a device trees and FIT image support for the Microsemi Jaguar2 SoC
which belongs to same family of the Ocelot SoC.
It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
.../devicetree/bindings/mips/mscc.txt | 2 +-
arch/mips/boot/dts/mscc/Makefile | 3 +
arch/mips/boot/dts/mscc/jaguar2.dtsi | 167 +++++++++++
arch/mips/boot/dts/mscc/jaguar2_common.dtsi | 25 ++
arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 273 ++++++++++++++++++
arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 109 +++++++
arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 59 ++++
arch/mips/generic/Kconfig | 8 +
arch/mips/generic/Platform | 1 +
arch/mips/generic/board-jaguar2.its.S | 40 +++
10 files changed, 686 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/mscc/jaguar2.dtsi
create mode 100644 arch/mips/boot/dts/mscc/jaguar2_common.dtsi
create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
create mode 100644 arch/mips/generic/board-jaguar2.its.S
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
index bdbebb525393..cc916eaeed0a 100644
--- a/Documentation/devicetree/bindings/mips/mscc.txt
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
-- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jaguar2"
+- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
* Other peripherals:
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index 40699b44ed50..befda72ceb26 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_SOC_VCOREIII) += \
+ jaguar2_pcb110.dtb \
+ jaguar2_pcb111.dtb \
+ jaguar2_pcb118.dtb \
luton_pcb091.dtb \
ocelot_pcb120.dtb \
ocelot_pcb123.dtb
diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi
new file mode 100644
index 000000000000..717018d75a33
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,jr2";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart2;
+ gpio0 = &gpio;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb: ahb@70000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
+
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,jaguar2-icpu-intr";
+ reg = <0x70000070 0x94>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@70100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@70100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@71070038 {
+ compatible = "mscc,jaguar2-pinctrl";
+ reg = <0x71010038 0x90>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 64>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_10", "GPIO_11";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_24", "GPIO_25";
+ function = "uart2";
+ };
+
+ cs1_pins: cs1-pins {
+ pins = "GPIO_16";
+ function = "si";
+ };
+
+ cs2_pins: cs2-pins {
+ pins = "GPIO_17";
+ function = "si";
+ };
+
+ cs3_pins: cs3-pins {
+ pins = "GPIO_18";
+ function = "si";
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_14", "GPIO_15";
+ function = "twi";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "GPIO_28", "GPIO_29";
+ function = "twi2";
+ };
+ };
+
+ i2c0: i2c@70100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x70100400 0x100>, <0x700001b8 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+
+ i2c2: i2c@70100c00 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ reg = <0x70100c00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/mscc/jaguar2_common.dtsi b/arch/mips/boot/dts/mscc/jaguar2_common.dtsi
new file mode 100644
index 000000000000..679ff0d8eda8
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/jaguar2_common.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+#include "jaguar2.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-sda-hold-time-ns = <300>;
+};
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
new file mode 100644
index 000000000000..306993ad9b4a
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "jaguar2_common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
+ compatible = "mscc,jr2-pcb110", "mscc,jr2";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c108 = &i2c108;
+ i2c109 = &i2c109;
+ i2c110 = &i2c110;
+ i2c111 = &i2c111;
+ i2c112 = &i2c112;
+ i2c113 = &i2c113;
+ i2c114 = &i2c114;
+ i2c115 = &i2c115;
+ i2c116 = &i2c116;
+ i2c117 = &i2c117;
+ i2c118 = &i2c118;
+ i2c119 = &i2c119;
+ i2c120 = &i2c120;
+ i2c121 = &i2c121;
+ i2c122 = &i2c122;
+ i2c123 = &i2c123;
+ i2c124 = &i2c124;
+ i2c125 = &i2c125;
+ i2c126 = &i2c126;
+ i2c127 = &i2c127;
+ i2c128 = &i2c128;
+ i2c129 = &i2c129;
+ i2c130 = &i2c130;
+ i2c131 = &i2c131;
+ i2c149 = &i2c149;
+ i2c150 = &i2c150;
+ i2c151 = &i2c151;
+ i2c152 = &i2c152;
+ };
+};
+
+&gpio {
+ synce_pins: synce-pins {
+ // GPIO 16 == SI_nCS1
+ pins = "GPIO_16";
+ function = "si";
+ };
+ synce_builtin_pins: synce-builtin-pins {
+ // GPIO 49 == SI_nCS13
+ pins = "GPIO_49";
+ function = "si";
+ };
+};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_21";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&i2c0 {
+ pca9545@70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+ i2c124: i2c_x2sfp_1_a@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ i2c125: i2c_x2sfp_1_b@1 {
+ /* FMC B */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c126: i2c_x2sfp_1_c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2c127: i2c_x2sfp_1_d@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ pca9545@71 {
+ compatible = "nxp,pca9545";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+ i2c128: i2c_x2sfp_1_a@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ i2c129: i2c_x2sfp_2_b@1 {
+ /* FMC B */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c130: i2c_x2sfp_3_c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2c131: i2c_x2sfp_4_d@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&ahb {
+ i2c0_emux: i2c0-emux@0 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH
+ &gpio 52 GPIO_ACTIVE_HIGH
+ &gpio 53 GPIO_ACTIVE_HIGH
+ &gpio 58 GPIO_ACTIVE_HIGH
+ &gpio 59 GPIO_ACTIVE_HIGH>;
+ idle-state = <0x0>;
+ i2c108: i2c_sfp9@10 {
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c109: i2c_sfp10@11 {
+ reg = <0x11>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c110: i2c_sfp11@12 {
+ reg = <0x12>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c111: i2c_sfp12@13 {
+ reg = <0x13>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c112: i2c_sfp13@14 {
+ reg = <0x14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c113: i2c_sfp14@15 {
+ reg = <0x15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c114: i2c_sfp15@16 {
+ reg = <0x16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c115: i2c_sfp16@17 {
+ reg = <0x17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c116: i2c_sfp17@8 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c117: i2c_sfp18@9 {
+ reg = <0x9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c118: i2c_sfp19@a {
+ reg = <0xa>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c119: i2c_sfp20@b {
+ reg = <0xb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c120: i2c_sfp21@c {
+ reg = <0xc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c121: i2c_sfp22@d {
+ reg = <0xd>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c122: i2c_sfp23@e {
+ reg = <0xe>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c123: i2c_sfp24@f {
+ reg = <0xf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c149", "i2c150", "i2c151", "i2c152", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_pins_i>;
+ i2c149: i2c_sfp_plus_a@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c150: i2c_sfp_plus_b@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c151: i2c_sfp_plus_c@2 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c152: i2c_sfp_plus_d@3 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
new file mode 100644
index 000000000000..df159dbb5a6c
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "jaguar2_common.dtsi"
+
+/ {
+ model = "Jaguar2 Cu48 PCB111 Reference Board";
+ compatible = "mscc,jr2-pcb111", "mscc,jr2";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c149 = &i2c149;
+ i2c150 = &i2c150;
+ i2c151 = &i2c151;
+ i2c152 = &i2c152;
+ i2c203 = &i2c203;
+ };
+};
+
+&gpio {
+ synce_builtin_pins: synce-builtin-pins {
+ // GPIO 49 == SI_nCS13
+ pins = "GPIO_49";
+ function = "si";
+ };
+ cpld_pins: cpld-pins {
+ // GPIO 50 == SI_nCS14
+ pins = "GPIO_50";
+ function = "si";
+ };
+ cpld_fifo_pins: synce-builtin-pins {
+ // GPIO 51 == SI_nCS15
+ pins = "GPIO_51";
+ function = "si";
+ };
+};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_17", "GPIO_18";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_21";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&ahb {
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
+ pinctrl-5 = <&i2cmux_pins_i>;
+ i2c149: i2c_sfp_plus_a@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c150: i2c_sfp_plus_b@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c151: i2c_sfp_plus_c@2 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c152: i2c_sfp_plus_d@3 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c203: i2c_pd69xxx@4 {
+ reg = <0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
new file mode 100644
index 000000000000..1b718a7b5ed9
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "jaguar2_common.dtsi"
+
+/ {
+ model = "Jaguar2/Aquantia PCB118 Reference Board";
+ compatible = "mscc,jr2-pcb118", "mscc,jr2";
+
+ aliases {
+ i2c150 = &i2c150;
+ i2c151 = &i2c151;
+ };
+};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_17", "GPIO_16";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_16";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&ahb {
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c150", "i2c151", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_pins_i>;
+ i2c150: i2c_sfp_plus_a@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c151: i2c_sfp_plus_b@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index e5a7a1314e71..c7a840b8eaa6 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -86,6 +86,14 @@ config FIT_IMAGE_FDT_LUTON
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
+config FIT_IMAGE_FDT_JAGUAR2
+ bool "Include FDT for Microsemi Jaguar2 development platforms"
+ select SOC_VCOREIII
+ help
+ Enable this to include the FDT for the Jaguar2 development platforms
+ from Microsemi in the FIT kernel image.
+ This requires u-boot on the platform.
+
config BOARD_INGENIC
bool "Support boards based on Ingenic SoCs"
select MACH_INGENIC_GENERIC
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index 4b6905daa39c..3f2055bea596 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -21,4 +21,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
diff --git a/arch/mips/generic/board-jaguar2.its.S b/arch/mips/generic/board-jaguar2.its.S
new file mode 100644
index 000000000000..fb0e589eeff7
--- /dev/null
+++ b/arch/mips/generic/board-jaguar2.its.S
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/ {
+ images {
+ fdt@jaguar2_pcb110 {
+ description = "MSCC Jaguar2 PCB110 Device Tree";
+ data = /incbin/("boot/dts/mscc/jaguar2_pcb110.dtb");
+ type = "flat_dt";
+ arch = "mips";
+ compression = "none";
+ hash@0 {
+ algo = "sha1";
+ };
+ };
+ fdt@jaguar2_pcb111 {
+ description = "MSCC Jaguar2 PCB111 Device Tree";
+ data = /incbin/("boot/dts/mscc/jaguar2_pcb111.dtb");
+ type = "flat_dt";
+ arch = "mips";
+ compression = "none";
+ hash@0 {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ pcb110 {
+ description = "Jaguar2 Linux kernel";
+ kernel = "kernel@0";
+ fdt = "fdt@jaguar2_pcb110";
+ ramdisk = "ramdisk";
+ };
+ pcb111 {
+ description = "Jaguar2 Linux kernel";
+ kernel = "kernel@0";
+ fdt = "fdt@jaguar2_pcb111";
+ ramdisk = "ramdisk";
+ };
+ };
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 8/9] MIPS: mscc: Add jaguar2 support
2020-11-06 10:08 ` [PATCH 8/9] MIPS: mscc: Add jaguar2 support Gregory CLEMENT
@ 2020-11-09 16:36 ` Gregory CLEMENT
2020-11-09 21:42 ` Rob Herring
1 sibling, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-09 16:36 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund
Hello,
> Add a device trees and FIT image support for the Microsemi Jaguar2 SoC
> which belongs to same family of the Ocelot SoC.
>
> It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
>
The i2c device node name are wrongs, I missed it for this submission and
will fix it in the next version.
For instance i2c_x2sfp_1_a@0 will be named i2c@0.
Gregory
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> .../devicetree/bindings/mips/mscc.txt | 2 +-
> arch/mips/boot/dts/mscc/Makefile | 3 +
> arch/mips/boot/dts/mscc/jaguar2.dtsi | 167 +++++++++++
> arch/mips/boot/dts/mscc/jaguar2_common.dtsi | 25 ++
> arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 273 ++++++++++++++++++
> arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 109 +++++++
> arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 59 ++++
> arch/mips/generic/Kconfig | 8 +
> arch/mips/generic/Platform | 1 +
> arch/mips/generic/board-jaguar2.its.S | 40 +++
> 10 files changed, 686 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2.dtsi
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_common.dtsi
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
> create mode 100644 arch/mips/generic/board-jaguar2.its.S
>
> diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
> index bdbebb525393..cc916eaeed0a 100644
> --- a/Documentation/devicetree/bindings/mips/mscc.txt
> +++ b/Documentation/devicetree/bindings/mips/mscc.txt
> @@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
> properties:
>
> Required properties:
> -- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jaguar2"
> +- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
>
>
> * Other peripherals:
> diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
> index 40699b44ed50..befda72ceb26 100644
> --- a/arch/mips/boot/dts/mscc/Makefile
> +++ b/arch/mips/boot/dts/mscc/Makefile
> @@ -1,5 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0-only
> dtb-$(CONFIG_SOC_VCOREIII) += \
> + jaguar2_pcb110.dtb \
> + jaguar2_pcb111.dtb \
> + jaguar2_pcb118.dtb \
> luton_pcb091.dtb \
> ocelot_pcb120.dtb \
> ocelot_pcb123.dtb
> diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi
> new file mode 100644
> index 000000000000..717018d75a33
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Microsemi Corporation
> + */
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "mscc,jr2";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart2;
> + gpio0 = &gpio;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "mips,mips24KEc";
> + device_type = "cpu";
> + clocks = <&cpu_clk>;
> + reg = <0>;
> + };
> + };
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + cpu_clk: cpu-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <500000000>;
> + };
> +
> + ahb_clk: ahb-clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&cpu_clk>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + ahb: ahb@70000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + interrupt-parent = <&intc>;
> +
> + cpu_ctrl: syscon@70000000 {
> + compatible = "mscc,ocelot-cpu-syscon", "syscon";
> + reg = <0x70000000 0x2c>;
> + };
> +
> + intc: interrupt-controller@70000070 {
> + compatible = "mscc,jaguar2-icpu-intr";
> + reg = <0x70000070 0x94>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + uart0: serial@70100000 {
> + pinctrl-0 = <&uart_pins>;
> + pinctrl-names = "default";
> + compatible = "ns16550a";
> + reg = <0x70100000 0x20>;
> + interrupts = <6>;
> + clocks = <&ahb_clk>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> +
> + status = "disabled";
> + };
> +
> + uart2: serial@70100800 {
> + pinctrl-0 = <&uart2_pins>;
> + pinctrl-names = "default";
> + compatible = "ns16550a";
> + reg = <0x70100800 0x20>;
> + interrupts = <7>;
> + clocks = <&ahb_clk>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> +
> + status = "disabled";
> + };
> +
> + gpio: pinctrl@71070038 {
> + compatible = "mscc,jaguar2-pinctrl";
> + reg = <0x71010038 0x90>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&gpio 0 0 64>;
> +
> + uart_pins: uart-pins {
> + pins = "GPIO_10", "GPIO_11";
> + function = "uart";
> + };
> +
> + uart2_pins: uart2-pins {
> + pins = "GPIO_24", "GPIO_25";
> + function = "uart2";
> + };
> +
> + cs1_pins: cs1-pins {
> + pins = "GPIO_16";
> + function = "si";
> + };
> +
> + cs2_pins: cs2-pins {
> + pins = "GPIO_17";
> + function = "si";
> + };
> +
> + cs3_pins: cs3-pins {
> + pins = "GPIO_18";
> + function = "si";
> + };
> +
> + i2c_pins: i2c-pins {
> + pins = "GPIO_14", "GPIO_15";
> + function = "twi";
> + };
> +
> + i2c2_pins: i2c2-pins {
> + pins = "GPIO_28", "GPIO_29";
> + function = "twi2";
> + };
> + };
> +
> + i2c0: i2c@70100400 {
> + compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
> + status = "disabled";
> + pinctrl-0 = <&i2c_pins>;
> + pinctrl-names = "default";
> + reg = <0x70100400 0x100>, <0x700001b8 0x8>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <8>;
> + clock-frequency = <100000>;
> + clocks = <&ahb_clk>;
> + };
> +
> + i2c2: i2c@70100c00 {
> + compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
> + status = "disabled";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-names = "default";
> + reg = <0x70100c00 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <8>;
> + clock-frequency = <100000>;
> + clocks = <&ahb_clk>;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/mscc/jaguar2_common.dtsi b/arch/mips/boot/dts/mscc/jaguar2_common.dtsi
> new file mode 100644
> index 000000000000..679ff0d8eda8
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/jaguar2_common.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Microsemi Corporation
> + */
> +
> +#include "jaguar2.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + i2c-sda-hold-time-ns = <300>;
> +};
> diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
> new file mode 100644
> index 000000000000..306993ad9b4a
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
> @@ -0,0 +1,273 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Microsemi Corporation
> + */
> +
> +/dts-v1/;
> +#include "jaguar2_common.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
> + compatible = "mscc,jr2-pcb110", "mscc,jr2";
> +
> + aliases {
> + i2c0 = &i2c0;
> + i2c108 = &i2c108;
> + i2c109 = &i2c109;
> + i2c110 = &i2c110;
> + i2c111 = &i2c111;
> + i2c112 = &i2c112;
> + i2c113 = &i2c113;
> + i2c114 = &i2c114;
> + i2c115 = &i2c115;
> + i2c116 = &i2c116;
> + i2c117 = &i2c117;
> + i2c118 = &i2c118;
> + i2c119 = &i2c119;
> + i2c120 = &i2c120;
> + i2c121 = &i2c121;
> + i2c122 = &i2c122;
> + i2c123 = &i2c123;
> + i2c124 = &i2c124;
> + i2c125 = &i2c125;
> + i2c126 = &i2c126;
> + i2c127 = &i2c127;
> + i2c128 = &i2c128;
> + i2c129 = &i2c129;
> + i2c130 = &i2c130;
> + i2c131 = &i2c131;
> + i2c149 = &i2c149;
> + i2c150 = &i2c150;
> + i2c151 = &i2c151;
> + i2c152 = &i2c152;
> + };
> +};
> +
> +&gpio {
> + synce_pins: synce-pins {
> + // GPIO 16 == SI_nCS1
> + pins = "GPIO_16";
> + function = "si";
> + };
> + synce_builtin_pins: synce-builtin-pins {
> + // GPIO 49 == SI_nCS13
> + pins = "GPIO_49";
> + function = "si";
> + };
> +};
> +
> +&gpio {
> + i2cmux_pins_i: i2cmux-pins-i {
> + pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
> + function = "twi_scl_m";
> + output-low;
> + };
> + i2cmux_0: i2cmux-0 {
> + pins = "GPIO_17";
> + function = "twi_scl_m";
> + output-high;
> + };
> + i2cmux_1: i2cmux-1 {
> + pins = "GPIO_18";
> + function = "twi_scl_m";
> + output-high;
> + };
> + i2cmux_2: i2cmux-2 {
> + pins = "GPIO_20";
> + function = "twi_scl_m";
> + output-high;
> + };
> + i2cmux_3: i2cmux-3 {
> + pins = "GPIO_21";
> + function = "twi_scl_m";
> + output-high;
> + };
> +};
> +
> +&i2c0 {
> + pca9545@70 {
> + compatible = "nxp,pca9545";
> + reg = <0x70>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect;
> + i2c124: i2c_x2sfp_1_a@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> + i2c125: i2c_x2sfp_1_b@1 {
> + /* FMC B */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + i2c126: i2c_x2sfp_1_c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> + i2c127: i2c_x2sfp_1_d@3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> + pca9545@71 {
> + compatible = "nxp,pca9545";
> + reg = <0x71>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-mux-idle-disconnect;
> + i2c128: i2c_x2sfp_1_a@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> + i2c129: i2c_x2sfp_2_b@1 {
> + /* FMC B */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + i2c130: i2c_x2sfp_3_c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + };
> + i2c131: i2c_x2sfp_4_d@3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + };
> + };
> +};
> +
> +&ahb {
> + i2c0_emux: i2c0-emux@0 {
> + compatible = "i2c-mux-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-parent = <&i2c0>;
> + mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH
> + &gpio 52 GPIO_ACTIVE_HIGH
> + &gpio 53 GPIO_ACTIVE_HIGH
> + &gpio 58 GPIO_ACTIVE_HIGH
> + &gpio 59 GPIO_ACTIVE_HIGH>;
> + idle-state = <0x0>;
> + i2c108: i2c_sfp9@10 {
> + reg = <0x10>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c109: i2c_sfp10@11 {
> + reg = <0x11>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c110: i2c_sfp11@12 {
> + reg = <0x12>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c111: i2c_sfp12@13 {
> + reg = <0x13>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c112: i2c_sfp13@14 {
> + reg = <0x14>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c113: i2c_sfp14@15 {
> + reg = <0x15>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c114: i2c_sfp15@16 {
> + reg = <0x16>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c115: i2c_sfp16@17 {
> + reg = <0x17>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c116: i2c_sfp17@8 {
> + reg = <0x8>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c117: i2c_sfp18@9 {
> + reg = <0x9>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c118: i2c_sfp19@a {
> + reg = <0xa>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c119: i2c_sfp20@b {
> + reg = <0xb>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c120: i2c_sfp21@c {
> + reg = <0xc>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c121: i2c_sfp22@d {
> + reg = <0xd>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c122: i2c_sfp23@e {
> + reg = <0xe>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c123: i2c_sfp24@f {
> + reg = <0xf>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + i2c0_imux: i2c0-imux@0 {
> + compatible = "i2c-mux-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-parent = <&i2c0>;
> + pinctrl-names =
> + "i2c149", "i2c150", "i2c151", "i2c152", "idle";
> + pinctrl-0 = <&i2cmux_0>;
> + pinctrl-1 = <&i2cmux_1>;
> + pinctrl-2 = <&i2cmux_2>;
> + pinctrl-3 = <&i2cmux_3>;
> + pinctrl-4 = <&i2cmux_pins_i>;
> + i2c149: i2c_sfp_plus_a@0 {
> + reg = <0x0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c150: i2c_sfp_plus_b@1 {
> + reg = <0x1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c151: i2c_sfp_plus_c@2 {
> + reg = <0x2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c152: i2c_sfp_plus_d@3 {
> + reg = <0x3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
> new file mode 100644
> index 000000000000..df159dbb5a6c
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
> @@ -0,0 +1,109 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +/dts-v1/;
> +#include "jaguar2_common.dtsi"
> +
> +/ {
> + model = "Jaguar2 Cu48 PCB111 Reference Board";
> + compatible = "mscc,jr2-pcb111", "mscc,jr2";
> +
> + aliases {
> + i2c0 = &i2c0;
> + i2c149 = &i2c149;
> + i2c150 = &i2c150;
> + i2c151 = &i2c151;
> + i2c152 = &i2c152;
> + i2c203 = &i2c203;
> + };
> +};
> +
> +&gpio {
> + synce_builtin_pins: synce-builtin-pins {
> + // GPIO 49 == SI_nCS13
> + pins = "GPIO_49";
> + function = "si";
> + };
> + cpld_pins: cpld-pins {
> + // GPIO 50 == SI_nCS14
> + pins = "GPIO_50";
> + function = "si";
> + };
> + cpld_fifo_pins: synce-builtin-pins {
> + // GPIO 51 == SI_nCS15
> + pins = "GPIO_51";
> + function = "si";
> + };
> +};
> +
> +&gpio {
> + i2cmux_pins_i: i2cmux-pins-i {
> + pins = "GPIO_17", "GPIO_18";
> + function = "twi_scl_m";
> + output-low;
> + };
> + i2cmux_0: i2cmux-0 {
> + pins = "GPIO_17";
> + function = "twi_scl_m";
> + output-high;
> + };
> + i2cmux_1: i2cmux-1 {
> + pins = "GPIO_18";
> + function = "twi_scl_m";
> + output-high;
> + };
> + i2cmux_2: i2cmux-2 {
> + pins = "GPIO_20";
> + function = "twi_scl_m";
> + output-high;
> + };
> + i2cmux_3: i2cmux-3 {
> + pins = "GPIO_21";
> + function = "twi_scl_m";
> + output-high;
> + };
> +};
> +
> +&ahb {
> + i2c0_imux: i2c0-imux@0 {
> + compatible = "i2c-mux-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-parent = <&i2c0>;
> + pinctrl-names =
> + "i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
> + pinctrl-0 = <&i2cmux_0>;
> + pinctrl-1 = <&i2cmux_1>;
> + pinctrl-2 = <&i2cmux_2>;
> + pinctrl-3 = <&i2cmux_3>;
> + pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
> + pinctrl-5 = <&i2cmux_pins_i>;
> + i2c149: i2c_sfp_plus_a@0 {
> + reg = <0x0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c150: i2c_sfp_plus_b@1 {
> + reg = <0x1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c151: i2c_sfp_plus_c@2 {
> + reg = <0x2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c152: i2c_sfp_plus_d@3 {
> + reg = <0x3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c203: i2c_pd69xxx@4 {
> + reg = <0x4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
> new file mode 100644
> index 000000000000..1b718a7b5ed9
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +/dts-v1/;
> +#include "jaguar2_common.dtsi"
> +
> +/ {
> + model = "Jaguar2/Aquantia PCB118 Reference Board";
> + compatible = "mscc,jr2-pcb118", "mscc,jr2";
> +
> + aliases {
> + i2c150 = &i2c150;
> + i2c151 = &i2c151;
> + };
> +};
> +
> +&gpio {
> + i2cmux_pins_i: i2cmux-pins-i {
> + pins = "GPIO_17", "GPIO_16";
> + function = "twi_scl_m";
> + output-low;
> + };
> + i2cmux_0: i2cmux-0 {
> + pins = "GPIO_17";
> + function = "twi_scl_m";
> + output-high;
> + };
> + i2cmux_1: i2cmux-1 {
> + pins = "GPIO_16";
> + function = "twi_scl_m";
> + output-high;
> + };
> +};
> +
> +&ahb {
> + i2c0_imux: i2c0-imux@0 {
> + compatible = "i2c-mux-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-parent = <&i2c0>;
> + pinctrl-names =
> + "i2c150", "i2c151", "idle";
> + pinctrl-0 = <&i2cmux_0>;
> + pinctrl-1 = <&i2cmux_1>;
> + pinctrl-2 = <&i2cmux_pins_i>;
> + i2c150: i2c_sfp_plus_a@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + i2c151: i2c_sfp_plus_b@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
> index e5a7a1314e71..c7a840b8eaa6 100644
> --- a/arch/mips/generic/Kconfig
> +++ b/arch/mips/generic/Kconfig
> @@ -86,6 +86,14 @@ config FIT_IMAGE_FDT_LUTON
> from Microsemi in the FIT kernel image.
> This requires u-boot on the platform.
>
> +config FIT_IMAGE_FDT_JAGUAR2
> + bool "Include FDT for Microsemi Jaguar2 development platforms"
> + select SOC_VCOREIII
> + help
> + Enable this to include the FDT for the Jaguar2 development platforms
> + from Microsemi in the FIT kernel image.
> + This requires u-boot on the platform.
> +
> config BOARD_INGENIC
> bool "Support boards based on Ingenic SoCs"
> select MACH_INGENIC_GENERIC
> diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
> index 4b6905daa39c..3f2055bea596 100644
> --- a/arch/mips/generic/Platform
> +++ b/arch/mips/generic/Platform
> @@ -21,4 +21,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
> its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
> its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
> its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S
> +its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S
> its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
> diff --git a/arch/mips/generic/board-jaguar2.its.S b/arch/mips/generic/board-jaguar2.its.S
> new file mode 100644
> index 000000000000..fb0e589eeff7
> --- /dev/null
> +++ b/arch/mips/generic/board-jaguar2.its.S
> @@ -0,0 +1,40 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/ {
> + images {
> + fdt@jaguar2_pcb110 {
> + description = "MSCC Jaguar2 PCB110 Device Tree";
> + data = /incbin/("boot/dts/mscc/jaguar2_pcb110.dtb");
> + type = "flat_dt";
> + arch = "mips";
> + compression = "none";
> + hash@0 {
> + algo = "sha1";
> + };
> + };
> + fdt@jaguar2_pcb111 {
> + description = "MSCC Jaguar2 PCB111 Device Tree";
> + data = /incbin/("boot/dts/mscc/jaguar2_pcb111.dtb");
> + type = "flat_dt";
> + arch = "mips";
> + compression = "none";
> + hash@0 {
> + algo = "sha1";
> + };
> + };
> + };
> +
> + configurations {
> + pcb110 {
> + description = "Jaguar2 Linux kernel";
> + kernel = "kernel@0";
> + fdt = "fdt@jaguar2_pcb110";
> + ramdisk = "ramdisk";
> + };
> + pcb111 {
> + description = "Jaguar2 Linux kernel";
> + kernel = "kernel@0";
> + fdt = "fdt@jaguar2_pcb111";
> + ramdisk = "ramdisk";
> + };
> + };
> +};
> --
> 2.28.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 8/9] MIPS: mscc: Add jaguar2 support
2020-11-06 10:08 ` [PATCH 8/9] MIPS: mscc: Add jaguar2 support Gregory CLEMENT
2020-11-09 16:36 ` Gregory CLEMENT
@ 2020-11-09 21:42 ` Rob Herring
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-11-09 21:42 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, devicetree, Thomas Petazzoni,
Lars Povlsen, Steen.Hegelund
On Fri, Nov 06, 2020 at 11:08:48AM +0100, Gregory CLEMENT wrote:
> Add a device trees and FIT image support for the Microsemi Jaguar2 SoC
> which belongs to same family of the Ocelot SoC.
>
> It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> .../devicetree/bindings/mips/mscc.txt | 2 +-
> arch/mips/boot/dts/mscc/Makefile | 3 +
> arch/mips/boot/dts/mscc/jaguar2.dtsi | 167 +++++++++++
> arch/mips/boot/dts/mscc/jaguar2_common.dtsi | 25 ++
> arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 273 ++++++++++++++++++
> arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 109 +++++++
> arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 59 ++++
> arch/mips/generic/Kconfig | 8 +
> arch/mips/generic/Platform | 1 +
> arch/mips/generic/board-jaguar2.its.S | 40 +++
> 10 files changed, 686 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2.dtsi
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_common.dtsi
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
> create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
> create mode 100644 arch/mips/generic/board-jaguar2.its.S
>
> diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
> index bdbebb525393..cc916eaeed0a 100644
> --- a/Documentation/devicetree/bindings/mips/mscc.txt
> +++ b/Documentation/devicetree/bindings/mips/mscc.txt
> @@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
> properties:
>
> Required properties:
> -- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jaguar2"
> +- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
Goes in patch 2.
>
>
> * Other peripherals:
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 9/9] MIPS: mscc: Add serval support
2020-11-06 10:08 [PATCH 0/9] MIPS: Add support for more mscc SoCs: Luton, Serval and Jaguar2 Gregory CLEMENT
` (8 preceding siblings ...)
2020-11-06 10:08 ` [PATCH 8/9] MIPS: mscc: Add jaguar2 support Gregory CLEMENT
@ 2020-11-06 10:08 ` Gregory CLEMENT
9 siblings, 0 replies; 16+ messages in thread
From: Gregory CLEMENT @ 2020-11-06 10:08 UTC (permalink / raw)
To: Alexandre Belloni, Microchip Linux Driver Support,
Thomas Bogendoerfer, linux-mips, Rob Herring, devicetree
Cc: Thomas Petazzoni, Lars Povlsen, Steen.Hegelund, Gregory CLEMENT
Add a device trees and FIT image support for the Microsemi Serval SoC
which belongs to same family of the Ocelot SoC.
It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/boot/dts/mscc/Makefile | 5 +-
arch/mips/boot/dts/mscc/serval.dtsi | 153 +++++++++++++++++++++
arch/mips/boot/dts/mscc/serval_common.dtsi | 127 +++++++++++++++++
arch/mips/boot/dts/mscc/serval_pcb105.dts | 17 +++
arch/mips/boot/dts/mscc/serval_pcb106.dts | 17 +++
arch/mips/generic/Kconfig | 8 ++
arch/mips/generic/Platform | 1 +
arch/mips/generic/board-serval.its.S | 24 ++++
8 files changed, 351 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/mscc/serval.dtsi
create mode 100644 arch/mips/boot/dts/mscc/serval_common.dtsi
create mode 100644 arch/mips/boot/dts/mscc/serval_pcb105.dts
create mode 100644 arch/mips/boot/dts/mscc/serval_pcb106.dts
create mode 100644 arch/mips/generic/board-serval.its.S
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index befda72ceb26..eeb6b7aae83b 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -5,6 +5,9 @@ dtb-$(CONFIG_SOC_VCOREIII) += \
jaguar2_pcb118.dtb \
luton_pcb091.dtb \
ocelot_pcb120.dtb \
- ocelot_pcb123.dtb
+ ocelot_pcb123.dtb \
+ serval_pcb105.dtb \
+ serval_pcb106.dtb
+
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/serval.dtsi b/arch/mips/boot/dts/mscc/serval.dtsi
new file mode 100644
index 000000000000..c357e2025d5a
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/serval.dtsi
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,serval";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ gpio0 = &gpio;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb: ahb@70000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
+
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,serval-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@70100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@70100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@71070034 {
+ compatible = "mscc,serval-pinctrl";
+ reg = <0x71070034 0x28>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
+ function = "sg0";
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_6", "GPIO_7";
+ function = "twi";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_26", "GPIO_27";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_13", "GPIO_14";
+ function = "uart2";
+ };
+
+ cs1_pins: cs1-pins {
+ pins = "GPIO_8";
+ function = "si";
+ };
+
+ irqext0_pins: irqext0-pins {
+ pins = "GPIO_28";
+ function = "irq0";
+ };
+
+ irqext1_pins: irqext1-pins {
+ pins = "GPIO_29";
+ function = "irq1";
+ };
+ };
+
+ i2c0: i2c@70100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x70100400 0x100>, <0x70000190 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi
new file mode 100644
index 000000000000..410236b6ee9b
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/serval_common.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+#include "serval.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ i2c104 = &i2c104;
+ i2c105 = &i2c105;
+ i2c106 = &i2c106;
+ i2c107 = &i2c107;
+ i2c108 = &i2c108;
+ i2c109 = &i2c109;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&gpio {
+ i2c_pins: i2c-pins {
+ pins = "GPIO_7"; /* No "default" scl for i2c0 */
+ function = "twi";
+ };
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
+ "GPIO_20", "GPIO_21";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_11";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_12";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_19";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_4: i2cmux-4 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_5: i2cmux-5 {
+ pins = "GPIO_21";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-sda-hold-time-ns = <300>;
+};
+
+&ahb {
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c104", "i2c105", "i2c106", "i2c107",
+ "i2c108", "i2c109", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_4>;
+ pinctrl-5 = <&i2cmux_5>;
+ pinctrl-6 = <&i2cmux_pins_i>;
+ i2c104: i2c_sfp0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c105: i2c_sfp1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c106: i2c_sfp2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c107: i2c_sfp3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c108: i2c_sfp4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c109: i2c_sfp5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/mscc/serval_pcb105.dts b/arch/mips/boot/dts/mscc/serval_pcb105.dts
new file mode 100644
index 000000000000..a1b0012b79d3
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/serval_pcb105.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "serval_common.dtsi"
+
+/ {
+ model = "Serval PCB105 Reference Board";
+ compatible = "mscc,serval-pcb105", "mscc,serval";
+
+ aliases {
+ };
+
+};
+
diff --git a/arch/mips/boot/dts/mscc/serval_pcb106.dts b/arch/mips/boot/dts/mscc/serval_pcb106.dts
new file mode 100644
index 000000000000..237be7c8da57
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/serval_pcb106.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "serval_common.dtsi"
+
+/ {
+ model = "Serval PCB106 Reference Board";
+ compatible = "mscc,serval-pcb106", "mscc,serval";
+
+ aliases {
+ };
+
+};
+
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index c7a840b8eaa6..657dd93c5e76 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -94,6 +94,14 @@ config FIT_IMAGE_FDT_JAGUAR2
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
+config FIT_IMAGE_FDT_SERVAL
+ bool "Include FDT for Microsemi Serval development platforms"
+ select SOC_VCOREIII
+ help
+ Enable this to include the FDT for the Serval development platforms
+ from Microsemi in the FIT kernel image.
+ This requires u-boot on the platform.
+
config BOARD_INGENIC
bool "Support boards based on Ingenic SoCs"
select MACH_INGENIC_GENERIC
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index 3f2055bea596..b871af16b5b6 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -22,4 +22,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S
its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_SERVAL) += board-serval.its.S
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
diff --git a/arch/mips/generic/board-serval.its.S b/arch/mips/generic/board-serval.its.S
new file mode 100644
index 000000000000..4ea4fc9d757f
--- /dev/null
+++ b/arch/mips/generic/board-serval.its.S
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/ {
+ images {
+ fdt@serval_pcb105 {
+ description = "MSCC Serval PCB105 Device Tree";
+ data = /incbin/("boot/dts/mscc/serval_pcb105.dtb");
+ type = "flat_dt";
+ arch = "mips";
+ compression = "none";
+ hash@0 {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ pcb105 {
+ description = "Serval Linux kernel";
+ kernel = "kernel@0";
+ fdt = "fdt@serval_pcb105";
+ ramdisk = "ramdisk";
+ };
+ };
+};
--
2.28.0
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