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From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: linux-staging@lists.linux.dev, gregkh@linuxfoundation.org,
	neil@brown.name, linux-mips@vger.kernel.org,
	ilya.lipnitskiy@gmail.com, john@phrozen.org
Subject: Re: [PATCH v2 1/3] MIPS: ralink: Define PCI_IOBASE
Date: Thu, 29 Jul 2021 12:01:46 +0200	[thread overview]
Message-ID: <20210729100146.GA8648@alpha.franken.de> (raw)
In-Reply-To: <20210614100617.28753-2-sergio.paracuellos@gmail.com>

On Mon, Jun 14, 2021 at 12:06:15PM +0200, Sergio Paracuellos wrote:
> PCI_IOBASE is used to create VM maps for PCI I/O ports, it is
> required by generic PCI drivers to make memory mapped I/O range
> work. Hence define it for ralink architectures to be able to
> avoid parsing manually IO ranges in PCI generic driver code.
> Function 'plat_mem_setup' for ralink is using 'set_io_port_base'
> call using '0xa0000000' as address, so use the same address in
> the definition to align things.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  arch/mips/include/asm/mach-ralink/spaces.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>  create mode 100644 arch/mips/include/asm/mach-ralink/spaces.h
> 
> diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h
> new file mode 100644
> index 000000000000..87d085c9ad61
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-ralink/spaces.h
> @@ -0,0 +1,10 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ASM_MACH_RALINK_SPACES_H_
> +#define __ASM_MACH_RALINK_SPACES_H_
> +
> +#define PCI_IOBASE	_AC(0xa0000000, UL)
> +#define PCI_IOSIZE	SZ_16M
> +#define IO_SPACE_LIMIT	(PCI_IOSIZE - 1)
> +
> +#include <asm/mach-generic/spaces.h>
> +#endif

does this really work for you ? I tried the same trick for RB532
and the generated IO addresses are wrong...

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

  parent reply	other threads:[~2021-07-29 10:02 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-14 10:06 [PATCH v2 0/3] staging: mt7621-pci: define ralink PCI_IOBASE to avoid manually ranges parsing Sergio Paracuellos
2021-06-14 10:06 ` [PATCH v2 1/3] MIPS: ralink: Define PCI_IOBASE Sergio Paracuellos
2021-06-15 11:51   ` Greg KH
2021-06-15 12:38     ` Sergio Paracuellos
2021-06-15 13:08   ` Thomas Bogendoerfer
2021-06-15 13:12     ` Sergio Paracuellos
2021-06-15 13:24       ` Greg KH
2021-07-29 10:01   ` Thomas Bogendoerfer [this message]
2021-07-29 11:21     ` Sergio Paracuellos
2021-07-30  8:30       ` Thomas Bogendoerfer
2021-07-30  9:41         ` Sergio Paracuellos
2021-07-30 10:22         ` Sergio Paracuellos
2021-07-30 11:15           ` Sergio Paracuellos
2021-07-30 12:39             ` Thomas Bogendoerfer
2021-07-30 15:51               ` Sergio Paracuellos
2021-06-14 10:06 ` [PATCH v2 2/3] staging: mt7621-pci: remove 'mt7621_pci_parse_request_of_pci_ranges' Sergio Paracuellos
2021-06-14 10:06 ` [PATCH v2 3/3] staging: mt7621-dts: fix pci address for PCI memory range Sergio Paracuellos

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