[PATCH 0/3] MIPS: BMIPS: add support for gated clock controller

[PATCH 0/3] MIPS: BMIPS: add support for gated clock controller

[Jonas Gorski]

This patchset adds support for the gated clock controller found on most
MIPS based Broadcom BCM63XX SoCs.

The MIPS based BCM63XX SoCs have very little in common with the ARM
based ones, so a separate driver is necessary.

It's a simple register based controller, with one bit per clock, active
high.

Since BCM63XX/MIPS runs in big endian mode, the driver depends on the
series "clk: make register endianness a run-time property", or more
specifically on patch 3, "clk: gate: add explicit big endian support".

Based on the clk-next branch.

Jonas Gorski (3):
  devicetree: document the BCM63XX gated clock bindings
  clk: add BCM63XX gated clock controller driver
  MIPS: BMIPS: add clock controller nodes

 .../bindings/clock/brcm,bcm63xx-clocks.txt         |  22 ++
 arch/mips/boot/dts/brcm/bcm3368.dtsi               |  12 +-
 arch/mips/boot/dts/brcm/bcm63268.dtsi              |  12 +-
 arch/mips/boot/dts/brcm/bcm6328.dtsi               |   6 +
 arch/mips/boot/dts/brcm/bcm6358.dtsi               |  12 +-
 arch/mips/boot/dts/brcm/bcm6362.dtsi               |  12 +-
 arch/mips/boot/dts/brcm/bcm6368.dtsi               |  12 +-
 drivers/clk/bcm/Kconfig                            |   8 +
 drivers/clk/bcm/Makefile                           |   1 +
 drivers/clk/bcm/clk-bcm63xx-gate.c                 | 246 +++++++++++++++++++++
 10 files changed, 328 insertions(+), 15 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
 create mode 100644 drivers/clk/bcm/clk-bcm63xx-gate.c

-- 
2.13.2

[PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Jonas Gorski]

Add binding documentation for the gated clock controller found on MIPS
based BCM63XX SoCs.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
 .../bindings/clock/brcm,bcm63xx-clocks.txt         | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt

diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
new file mode 100644
index 000000000000..3041657e2f96
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
@@ -0,0 +1,22 @@
+Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
+
+Required properties:
+- compatible: must be one of:
+	 "brcm,bcm3368-clocks"
+	 "brcm,bcm6328-clocks"
+	 "brcm,bcm6358-clocks"
+	 "brcm,bcm6362-clocks"
+	 "brcm,bcm6368-clocks"
+	 "brcm,bcm63268-clocks"
+
+- reg: Address and length of the register set
+- #clock-cells: must be <1>
+
+
+Example:
+
+clkctl: clock-controller@10000004 {
+	compatible = "brcm,bcm6328-clocks";
+	reg = <0x10000004 0x4>;
+	#clock-cells = <1>;
+};
-- 
2.13.2

Re: [PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Florian Fainelli]

On 5/2/2019 5:26 AM, Jonas Gorski wrote:
> Add binding documentation for the gated clock controller found on MIPS
> based BCM63XX SoCs.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

> ---
>  .../bindings/clock/brcm,bcm63xx-clocks.txt         | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> new file mode 100644
> index 000000000000..3041657e2f96
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> @@ -0,0 +1,22 @@
> +Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
> +
> +Required properties:
> +- compatible: must be one of:
> +	 "brcm,bcm3368-clocks"
> +	 "brcm,bcm6328-clocks"
> +	 "brcm,bcm6358-clocks"
> +	 "brcm,bcm6362-clocks"
> +	 "brcm,bcm6368-clocks"
> +	 "brcm,bcm63268-clocks"

We could always add 6348/6338 to that list later one.

> +
> +- reg: Address and length of the register set
> +- #clock-cells: must be <1>
> +
> +
> +Example:
> +
> +clkctl: clock-controller@10000004 {
> +	compatible = "brcm,bcm6328-clocks";
> +	reg = <0x10000004 0x4>;
> +	#clock-cells = <1>;
> +};
> 

-- 
Florian

Re: [PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Jonas Gorski]

On Fri, 3 May 2019 at 03:44, Florian Fainelli <f.fainelli@gmail.com> wrote:
>
>
>
> On 5/2/2019 5:26 AM, Jonas Gorski wrote:
> > Add binding documentation for the gated clock controller found on MIPS
> > based BCM63XX SoCs.
> >
> > Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

Thanks!

>
> > ---
> >  .../bindings/clock/brcm,bcm63xx-clocks.txt         | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> >
> > diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> > new file mode 100644
> > index 000000000000..3041657e2f96
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> > @@ -0,0 +1,22 @@
> > +Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
> > +
> > +Required properties:
> > +- compatible: must be one of:
> > +      "brcm,bcm3368-clocks"
> > +      "brcm,bcm6328-clocks"
> > +      "brcm,bcm6358-clocks"
> > +      "brcm,bcm6362-clocks"
> > +      "brcm,bcm6368-clocks"
> > +      "brcm,bcm63268-clocks"
>
> We could always add 6348/6338 to that list later one.

That's the plan*. But currently neither one is supported by
BMIPS_GENERIC, which was my starting point. And making BCM63XX use the
driver is ... complicated, due to (important) consumers not being
platform drivers (the MPI/PCIe controller codes). And they can't be
just converted to platform drivers, as they should then be non-legacy
PCI controller drivers, so a full rewrite is needed.

So let's stick with BMIPS_GENERIC first, else we never get anything
done ;-). In the end BCM63XX should go away anyway, once BMIPS_GENERIC
has reached feature parity.


Regards
Jonas

* if it even makes sense, as these are quite old, and systems will
quite struggle running a modern kernel/OS.

Jonas

Re: [PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Philippe Mathieu-Daudé]

Hi Jonas,

On 5/2/19 2:26 PM, Jonas Gorski wrote:
> Add binding documentation for the gated clock controller found on MIPS
> based BCM63XX SoCs.

I'd have ordered this patch after the #2 of this series, or eventually
squashed both together. It is weird to document an unexistant feature
then implement it, while the opposite looks more natural.
(If you agree, maybe Paul can invert those when applying this series).

Anyway:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> ---
>  .../bindings/clock/brcm,bcm63xx-clocks.txt         | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> new file mode 100644
> index 000000000000..3041657e2f96
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> @@ -0,0 +1,22 @@
> +Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
> +
> +Required properties:
> +- compatible: must be one of:
> +	 "brcm,bcm3368-clocks"
> +	 "brcm,bcm6328-clocks"
> +	 "brcm,bcm6358-clocks"
> +	 "brcm,bcm6362-clocks"
> +	 "brcm,bcm6368-clocks"
> +	 "brcm,bcm63268-clocks"
> +
> +- reg: Address and length of the register set
> +- #clock-cells: must be <1>
> +
> +
> +Example:
> +
> +clkctl: clock-controller@10000004 {
> +	compatible = "brcm,bcm6328-clocks";
> +	reg = <0x10000004 0x4>;
> +	#clock-cells = <1>;
> +};
> 

Re: [PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Jonas Gorski]

Hi Philippe,

On Fri, 3 May 2019 at 16:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Jonas,
>
> On 5/2/19 2:26 PM, Jonas Gorski wrote:
> > Add binding documentation for the gated clock controller found on MIPS
> > based BCM63XX SoCs.
>
> I'd have ordered this patch after the #2 of this series, or eventually
> squashed both together. It is weird to document an unexistant feature
> then implement it, while the opposite looks more natural.
> (If you agree, maybe Paul can invert those when applying this series).
>
> Anyway:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

You are documenting hardware, not a driver/feature. :-)

The binding is supposed to be a separate patch [1]. The natural order
is to first describe the hardware (with the binding documentation),
then add the actual driver making use of the binding. Checkpatch.pl
will also warn if you use a compatible that isn't documented, which
happens (shortly) if you first add the driver.


Regards
Jonas

[1] https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/submitting-patches.txt#L8

Re: [PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Philippe Mathieu-Daudé]

On 5/5/19 8:57 PM, Jonas Gorski wrote:
> Hi Philippe,
> 
> On Fri, 3 May 2019 at 16:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> Hi Jonas,
>>
>> On 5/2/19 2:26 PM, Jonas Gorski wrote:
>>> Add binding documentation for the gated clock controller found on MIPS
>>> based BCM63XX SoCs.
>>
>> I'd have ordered this patch after the #2 of this series, or eventually
>> squashed both together. It is weird to document an unexistant feature
>> then implement it, while the opposite looks more natural.
>> (If you agree, maybe Paul can invert those when applying this series).
>>
>> Anyway:
>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> You are documenting hardware, not a driver/feature. :-)
> 
> The binding is supposed to be a separate patch [1]. The natural order
> is to first describe the hardware (with the binding documentation),
> then add the actual driver making use of the binding. Checkpatch.pl
> will also warn if you use a compatible that isn't documented, which
> happens (shortly) if you first add the driver.

Oh, thanks for the pointer, this is my first DT review ;)

> Regards
> Jonas
> 
> [1] https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/submitting-patches.txt#L8
> 

Re: [PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Rob Herring]

On Thu,  2 May 2019 14:26:55 +0200, Jonas Gorski wrote:
> Add binding documentation for the gated clock controller found on MIPS
> based BCM63XX SoCs.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> ---
>  .../bindings/clock/brcm,bcm63xx-clocks.txt         | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/3] devicetree: document the BCM63XX gated clock bindings

[Stephen Boyd]

Quoting Jonas Gorski (2019-05-02 05:26:55)
> Add binding documentation for the gated clock controller found on MIPS
> based BCM63XX SoCs.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> ---

Applied to clk-next

[PATCH 2/3] clk: add BCM63XX gated clock controller driver

[Jonas Gorski]

Add a driver for the gated clock controller found on MIPS based BCM63XX
SoCs.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
 drivers/clk/bcm/Kconfig            |   8 ++
 drivers/clk/bcm/Makefile           |   1 +
 drivers/clk/bcm/clk-bcm63xx-gate.c | 246 +++++++++++++++++++++++++++++++++++++
 3 files changed, 255 insertions(+)
 create mode 100644 drivers/clk/bcm/clk-bcm63xx-gate.c

diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 4c4bd85f707c..144e724815c6 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -7,6 +7,14 @@ config CLK_BCM_63XX
 	  Enable common clock framework support for Broadcom BCM63xx DSL SoCs
 	  based on the ARM architecture
 
+config CLK_BCM_63XX_GATE
+	bool "Broadcom BCM63xx gated clock support"
+	depends on BMIPS_GENERIC || COMPILE_TEST
+	default BMIPS_GENERIC
+	help
+	  Enable common clock framework support for Broadcom BCM63xx DSL SoCs
+	  based on the MIPS architecture
+
 config CLK_BCM_KONA
 	bool "Broadcom Kona CCU clock support"
 	depends on ARCH_BCM_MOBILE || COMPILE_TEST
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 002661d39128..3d925493db7f 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_CLK_BCM_63XX)	+= clk-bcm63xx.o
+obj-$(CONFIG_CLK_BCM_63XX_GATE)	+= clk-bcm63xx-gate.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona-setup.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm281xx.o
diff --git a/drivers/clk/bcm/clk-bcm63xx-gate.c b/drivers/clk/bcm/clk-bcm63xx-gate.c
new file mode 100644
index 000000000000..4fd10645a192
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm63xx-gate.c
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+struct clk_bcm63xx_table_entry {
+	const char * const name;
+	u8 bit;
+	unsigned long flags;
+};
+
+struct clk_bcm63xx_hw {
+	void __iomem *regs;
+	spinlock_t lock;
+
+	struct clk_hw_onecell_data data;
+};
+
+const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
+	{ .name = "mac", .bit = 3, },
+	{ .name = "tc", .bit = 5, },
+	{ .name = "us_top", .bit = 6, },
+	{ .name = "ds_top", .bit = 7, },
+	{ .name = "acm", .bit = 8, },
+	{ .name = "spi", .bit = 9, },
+	{ .name = "usbs", .bit = 10, },
+	{ .name = "bmu", .bit = 11, },
+	{ .name = "pcm", .bit = 12, },
+	{ .name = "ntp", .bit = 13, },
+	{ .name = "acp_b", .bit = 14, },
+	{ .name = "acp_a", .bit = 15, },
+	{ .name = "emusb", .bit = 17, },
+	{ .name = "enet0", .bit = 18, },
+	{ .name = "enet1", .bit = 19, },
+	{ .name = "usbsu", .bit = 20, },
+	{ .name = "ephy", .bit = 21, },
+	{ },
+};
+
+const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
+	{ .name = "phy_mips", .bit = 0, },
+	{ .name = "adsl_qproc", .bit = 1, },
+	{ .name = "adsl_afe", .bit = 2, },
+	{ .name = "adsl", .bit = 3, },
+	{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
+	{ .name = "sar", .bit = 5, },
+	{ .name = "pcm", .bit = 6, },
+	{ .name = "usbd", .bit = 7, },
+	{ .name = "usbh", .bit = 8, },
+	{ .name = "hsspi", .bit = 9, },
+	{ .name = "pcie", .bit = 10, },
+	{ .name = "robosw", .bit = 11, },
+	{ },
+};
+
+const struct clk_bcm63xx_table_entry bcm6358_clocks[] = {
+	{ .name = "enet", .bit = 4, },
+	{ .name = "adslphy", .bit = 5, },
+	{ .name = "pcm", .bit = 8, },
+	{ .name = "spi", .bit = 9, },
+	{ .name = "usbs", .bit = 10, },
+	{ .name = "sar", .bit = 11, },
+	{ .name = "emusb", .bit = 17, },
+	{ .name = "enet0", .bit = 18, },
+	{ .name = "enet1", .bit = 19, },
+	{ .name = "usbsu", .bit = 20, },
+	{ .name = "ephy", .bit = 21, },
+	{ },
+};
+
+const struct clk_bcm63xx_table_entry bcm6362_clocks[] = {
+	{ .name = "adsl_qproc", .bit = 1, },
+	{ .name = "adsl_afe", .bit = 2, },
+	{ .name = "adsl", .bit = 3, },
+	{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
+	{ .name = "wlan_ocp", .bit = 5, },
+	{ .name = "swpkt_usb", .bit = 7, },
+	{ .name = "swpkt_sar", .bit = 8, },
+	{ .name = "sar", .bit = 9, },
+	{ .name = "robosw", .bit = 10, },
+	{ .name = "pcm", .bit = 11, },
+	{ .name = "usbd", .bit = 12, },
+	{ .name = "usbh", .bit = 13, },
+	{ .name = "ipsec", .bit = 14, },
+	{ .name = "spi", .bit = 15, },
+	{ .name = "hsspi", .bit = 16, },
+	{ .name = "pcie", .bit = 17, },
+	{ .name = "fap", .bit = 18, },
+	{ .name = "phymips", .bit = 19, },
+	{ .name = "nand", .bit = 20, },
+	{ },
+};
+
+const struct clk_bcm63xx_table_entry bcm6368_clocks[] = {
+	{ .name = "vdsl_qproc", .bit = 2, },
+	{ .name = "vdsl_afe", .bit = 3, },
+	{ .name = "vdsl_bonding", .bit = 4, },
+	{ .name = "vdsl", .bit = 5, },
+	{ .name = "phymips", .bit = 6, },
+	{ .name = "swpkt_usb", .bit = 7, },
+	{ .name = "swpkt_sar", .bit = 8, },
+	{ .name = "spi", .bit = 9, },
+	{ .name = "usbd", .bit = 10, },
+	{ .name = "sar", .bit = 11, },
+	{ .name = "robosw", .bit = 12, },
+	{ .name = "utopia", .bit = 13, },
+	{ .name = "pcm", .bit = 14, },
+	{ .name = "usbh", .bit = 15, },
+	{ .name = "disable_gless", .bit = 16, },
+	{ .name = "nand", .bit = 17, },
+	{ .name = "ipsec", .bit = 18, },
+	{ },
+};
+
+const struct clk_bcm63xx_table_entry bcm63268_clocks[] = {
+	{ .name = "disable_gless", .bit = 0, },
+	{ .name = "vdsl_qproc", .bit = 1, },
+	{ .name = "vdsl_afe", .bit = 2, },
+	{ .name = "vdsl", .bit = 3, },
+	{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
+	{ .name = "wlan_ocp", .bit = 5, },
+	{ .name = "dect", .bit = 6, },
+	{ .name = "fap0", .bit = 7, },
+	{ .name = "fap1", .bit = 8, },
+	{ .name = "sar", .bit = 9, },
+	{ .name = "robosw", .bit = 10, },
+	{ .name = "pcm", .bit = 11, },
+	{ .name = "usbd", .bit = 12, },
+	{ .name = "usbh", .bit = 13, },
+	{ .name = "ipsec", .bit = 14, },
+	{ .name = "spi", .bit = 15, },
+	{ .name = "hsspi", .bit = 16, },
+	{ .name = "pcie", .bit = 17, },
+	{ .name = "phymips", .bit = 18, },
+	{ .name = "gmac", .bit = 19, },
+	{ .name = "nand", .bit = 20, },
+	{ .name = "tbus", .bit = 27, },
+	{ .name = "robosw250", .bit = 31, },
+	{ },
+};
+
+static int clk_bcm63xx_probe(struct platform_device *pdev)
+{
+	const struct clk_bcm63xx_table_entry *entry, *table;
+	struct clk_bcm63xx_hw *hw;
+	struct resource *r;
+	u8 maxbit = 0;
+	int i, ret;
+
+	table = of_device_get_match_data(&pdev->dev);
+	if (!table)
+		return -EINVAL;
+
+	for (entry = table; entry->name; entry++)
+		maxbit = max_t(u8, maxbit, entry->bit);
+
+	hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
+			  GFP_KERNEL);
+	if (!hw)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, hw);
+
+	spin_lock_init(&hw->lock);
+
+	hw->data.num = maxbit;
+	for (i = 0; i < maxbit; i++)
+		hw->data.hws[i] = ERR_PTR(-ENODEV);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hw->regs = devm_ioremap_resource(&pdev->dev, r);
+	if (IS_ERR(hw->regs))
+		return PTR_ERR(hw->regs);
+
+	for (entry = table; entry->name; entry++) {
+		struct clk_hw *clk;
+
+		clk = clk_hw_register_gate(&pdev->dev, entry->name, NULL,
+					   entry->flags, hw->regs, entry->bit,
+					   CLK_GATE_BIG_ENDIAN, &hw->lock);
+		if (IS_ERR(clk)) {
+			ret = PTR_ERR(clk);
+			goto out_err;
+		}
+
+		hw->data.hws[entry->bit] = clk;
+	}
+
+	ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
+				     &hw->data);
+	if (!ret)
+		return 0;
+out_err:
+	for (i = 0; i < hw->data.num; i++) {
+		if (!IS_ERR(hw->data.hws[i]))
+			clk_hw_unregister_gate(hw->data.hws[i]);
+	}
+
+	return ret;
+}
+
+static int clk_bcm63xx_remove(struct platform_device *pdev)
+{
+	struct clk_bcm63xx_hw *hw = platform_get_drvdata(pdev);
+	int i;
+
+	of_clk_del_provider(pdev->dev.of_node);
+
+	for (i = 0; i < hw->data.num; i++) {
+		if (!IS_ERR(hw->data.hws[i]))
+			clk_hw_unregister_gate(hw->data.hws[i]);
+	}
+
+	return 0;
+}
+
+static const struct of_device_id clk_bcm63xx_dt_ids[] = {
+	{ .compatible = "brcm,bcm3368-clocks", .data = &bcm3368_clocks, },
+	{ .compatible = "brcm,bcm6328-clocks", .data = &bcm6328_clocks, },
+	{ .compatible = "brcm,bcm6358-clocks", .data = &bcm6358_clocks, },
+	{ .compatible = "brcm,bcm6362-clocks", .data = &bcm6362_clocks, },
+	{ .compatible = "brcm,bcm6368-clocks", .data = &bcm6368_clocks, },
+	{ .compatible = "brcm,bcm63268-clocks", .data = &bcm63268_clocks, },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(of, clk_bcm63xx_dt_ids);
+
+static struct platform_driver clk_bcm63xx = {
+	.probe = clk_bcm63xx_probe,
+	.remove = clk_bcm63xx_remove,
+	.driver = {
+		.name = "bcm63xx-clock",
+		.of_match_table = of_match_ptr(clk_bcm63xx_dt_ids),
+	},
+};
+
+builtin_platform_driver(clk_bcm63xx);
+
+MODULE_AUTHOR("Jonas Gorski <jonas.gorski@gmail.com>");
+MODULE_DESCRIPTION("BCM63XX (MIPS) gated clock controller driver");
+MODULE_LICENSE("GPL");
-- 
2.13.2

Re: [PATCH 2/3] clk: add BCM63XX gated clock controller driver

[Florian Fainelli]

On 5/2/2019 5:26 AM, Jonas Gorski wrote:
> Add a driver for the gated clock controller found on MIPS based BCM63XX
> SoCs.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 2/3] clk: add BCM63XX gated clock controller driver

[Philippe Mathieu-Daudé]

On 5/2/19 2:26 PM, Jonas Gorski wrote:
> Add a driver for the gated clock controller found on MIPS based BCM63XX
> SoCs.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH 2/3] clk: add BCM63XX gated clock controller driver

[Stephen Boyd]

Quoting Jonas Gorski (2019-05-02 05:26:56)
> Add a driver for the gated clock controller found on MIPS based BCM63XX
> SoCs.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> ---

Applied to clk-next with some extra fixes

diff --git a/drivers/clk/bcm/clk-bcm63xx-gate.c b/drivers/clk/bcm/clk-bcm63xx-gate.c
index 4fd10645a192..9e1dcd43258c 100644
--- a/drivers/clk/bcm/clk-bcm63xx-gate.c
+++ b/drivers/clk/bcm/clk-bcm63xx-gate.c
@@ -1,8 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
 
 #include <linux/clk-provider.h>
 #include <linux/init.h>
-#include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
@@ -20,7 +19,7 @@ struct clk_bcm63xx_hw {
 	struct clk_hw_onecell_data data;
 };
 
-const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
+static const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
 	{ .name = "mac", .bit = 3, },
 	{ .name = "tc", .bit = 5, },
 	{ .name = "us_top", .bit = 6, },
@@ -41,7 +40,7 @@ const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
 	{ },
 };
 
-const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
+static const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
 	{ .name = "phy_mips", .bit = 0, },
 	{ .name = "adsl_qproc", .bit = 1, },
 	{ .name = "adsl_afe", .bit = 2, },
@@ -57,7 +56,7 @@ const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
 	{ },
 };
 
-const struct clk_bcm63xx_table_entry bcm6358_clocks[] = {
+static const struct clk_bcm63xx_table_entry bcm6358_clocks[] = {
 	{ .name = "enet", .bit = 4, },
 	{ .name = "adslphy", .bit = 5, },
 	{ .name = "pcm", .bit = 8, },
@@ -72,7 +71,7 @@ const struct clk_bcm63xx_table_entry bcm6358_clocks[] = {
 	{ },
 };
 
-const struct clk_bcm63xx_table_entry bcm6362_clocks[] = {
+static const struct clk_bcm63xx_table_entry bcm6362_clocks[] = {
 	{ .name = "adsl_qproc", .bit = 1, },
 	{ .name = "adsl_afe", .bit = 2, },
 	{ .name = "adsl", .bit = 3, },
@@ -95,7 +94,7 @@ const struct clk_bcm63xx_table_entry bcm6362_clocks[] = {
 	{ },
 };
 
-const struct clk_bcm63xx_table_entry bcm6368_clocks[] = {
+static const struct clk_bcm63xx_table_entry bcm6368_clocks[] = {
 	{ .name = "vdsl_qproc", .bit = 2, },
 	{ .name = "vdsl_afe", .bit = 3, },
 	{ .name = "vdsl_bonding", .bit = 4, },
@@ -116,7 +115,7 @@ const struct clk_bcm63xx_table_entry bcm6368_clocks[] = {
 	{ },
 };
 
-const struct clk_bcm63xx_table_entry bcm63268_clocks[] = {
+static const struct clk_bcm63xx_table_entry bcm63268_clocks[] = {
 	{ .name = "disable_gless", .bit = 0, },
 	{ .name = "vdsl_qproc", .bit = 1, },
 	{ .name = "vdsl_afe", .bit = 2, },
@@ -225,22 +224,15 @@ static const struct of_device_id clk_bcm63xx_dt_ids[] = {
 	{ .compatible = "brcm,bcm6362-clocks", .data = &bcm6362_clocks, },
 	{ .compatible = "brcm,bcm6368-clocks", .data = &bcm6368_clocks, },
 	{ .compatible = "brcm,bcm63268-clocks", .data = &bcm63268_clocks, },
-	{ },
+	{ }
 };
 
-MODULE_DEVICE_TABLE(of, clk_bcm63xx_dt_ids);
-
 static struct platform_driver clk_bcm63xx = {
 	.probe = clk_bcm63xx_probe,
 	.remove = clk_bcm63xx_remove,
 	.driver = {
 		.name = "bcm63xx-clock",
-		.of_match_table = of_match_ptr(clk_bcm63xx_dt_ids),
+		.of_match_table = clk_bcm63xx_dt_ids,
 	},
 };
-
 builtin_platform_driver(clk_bcm63xx);
-
-MODULE_AUTHOR("Jonas Gorski <jonas.gorski@gmail.com>");
-MODULE_DESCRIPTION("BCM63XX (MIPS) gated clock controller driver");
-MODULE_LICENSE("GPL");

[PATCH 3/3] MIPS: BMIPS: add clock controller nodes

[Jonas Gorski]

Now that we have a driver for the clock controller, add nodes to allow
devices to make use of it.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm3368.dtsi  | 12 +++++++++---
 arch/mips/boot/dts/brcm/bcm63268.dtsi | 12 +++++++++---
 arch/mips/boot/dts/brcm/bcm6328.dtsi  |  6 ++++++
 arch/mips/boot/dts/brcm/bcm6358.dtsi  | 12 +++++++++---
 arch/mips/boot/dts/brcm/bcm6362.dtsi  | 12 +++++++++---
 arch/mips/boot/dts/brcm/bcm6368.dtsi  | 12 +++++++++---
 6 files changed, 51 insertions(+), 15 deletions(-)

diff --git a/arch/mips/boot/dts/brcm/bcm3368.dtsi b/arch/mips/boot/dts/brcm/bcm3368.dtsi
index 7a3e5c8943ca..69cbef472377 100644
--- a/arch/mips/boot/dts/brcm/bcm3368.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm3368.dtsi
@@ -51,16 +51,22 @@
 		compatible = "simple-bus";
 		ranges;
 
-		periph_cntl: syscon@fff8c000 {
+		clkctl: clock-controller@fff8c004 {
+			compatible = "brcm,bcm3368-clocks";
+			reg = <0xfff8c004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_cntl: syscon@fff8c008 {
 			compatible = "syscon";
-			reg = <0xfff8c000 0xc>;
+			reg = <0xfff8c000 0x4>;
 			native-endian;
 		};
 
 		reboot: syscon-reboot@fff8c008 {
 			compatible = "syscon-reboot";
 			regmap = <&periph_cntl>;
-			offset = <0x8>;
+			offset = <0x0>;
 			mask = <0x1>;
 		};
 
diff --git a/arch/mips/boot/dts/brcm/bcm63268.dtsi b/arch/mips/boot/dts/brcm/bcm63268.dtsi
index 58790b173bb2..beec24145af7 100644
--- a/arch/mips/boot/dts/brcm/bcm63268.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi
@@ -51,16 +51,22 @@
 		compatible = "simple-bus";
 		ranges;
 
-		periph_cntl: syscon@10000000 {
+		clkctl: clock-controller@10000004 {
+			compatible = "brcm,bcm63268-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_cntl: syscon@10000008 {
 			compatible = "syscon";
-			reg = <0x10000000 0x14>;
+			reg = <0x10000000 0xc>;
 			native-endian;
 		};
 
 		reboot: syscon-reboot@10000008 {
 			compatible = "syscon-reboot";
 			regmap = <&periph_cntl>;
-			offset = <0x8>;
+			offset = <0x0>;
 			mask = <0x1>;
 		};
 
diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi
index bf6716aa425a..af860d06def6 100644
--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
@@ -51,6 +51,12 @@
 		compatible = "simple-bus";
 		ranges;
 
+		clkctl: clock-controller@10000004 {
+			compatible = "brcm,bcm6328-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
 		periph_intc: interrupt-controller@10000020 {
 			compatible = "brcm,bcm6345-l1-intc";
 			reg = <0x10000020 0x10>,
diff --git a/arch/mips/boot/dts/brcm/bcm6358.dtsi b/arch/mips/boot/dts/brcm/bcm6358.dtsi
index 26ddae5a4247..f21176cac038 100644
--- a/arch/mips/boot/dts/brcm/bcm6358.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi
@@ -51,16 +51,22 @@
 		compatible = "simple-bus";
 		ranges;
 
-		periph_cntl: syscon@fffe0000 {
+		clkctl: clock-controller@fffe0004 {
+			compatible = "brcm,bcm6358-clocks";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_cntl: syscon@fffe0008 {
 			compatible = "syscon";
-			reg = <0xfffe0000 0xc>;
+			reg = <0xfffe0000 0x4>;
 			native-endian;
 		};
 
 		reboot: syscon-reboot@fffe0008 {
 			compatible = "syscon-reboot";
 			regmap = <&periph_cntl>;
-			offset = <0x8>;
+			offset = <0x0>;
 			mask = <0x1>;
 		};
 
diff --git a/arch/mips/boot/dts/brcm/bcm6362.dtsi b/arch/mips/boot/dts/brcm/bcm6362.dtsi
index c387793525dd..8ae6981735b8 100644
--- a/arch/mips/boot/dts/brcm/bcm6362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi
@@ -51,16 +51,22 @@
 		compatible = "simple-bus";
 		ranges;
 
-		periph_cntl: syscon@10000000 {
+		clkctl: clock-controller@10000004 {
+			compatible = "brcm,bcm6362-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_cntl: syscon@10000008 {
 			compatible = "syscon";
-			reg = <0x10000000 0x14>;
+			reg = <0x10000000 0xc>;
 			native-endian;
 		};
 
 		reboot: syscon-reboot@10000008 {
 			compatible = "syscon-reboot";
 			regmap = <&periph_cntl>;
-			offset = <0x8>;
+			offset = <0x0>;
 			mask = <0x1>;
 		};
 
diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi
index e116a385525f..449c167dd892 100644
--- a/arch/mips/boot/dts/brcm/bcm6368.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi
@@ -51,16 +51,22 @@
 		compatible = "simple-bus";
 		ranges;
 
-		periph_cntl: syscon@10000000 {
+		clkctl: clock-controller@10000004 {
+			compatible = "brcm,bcm6368-clocks";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_cntl: syscon@100000008 {
 			compatible = "syscon";
-			reg = <0x10000000 0x14>;
+			reg = <0x10000000 0xc>;
 			native-endian;
 		};
 
 		reboot: syscon-reboot@10000008 {
 			compatible = "syscon-reboot";
 			regmap = <&periph_cntl>;
-			offset = <0x8>;
+			offset = <0x0>;
 			mask = <0x1>;
 		};
 
-- 
2.13.2

Re: [PATCH 3/3] MIPS: BMIPS: add clock controller nodes

[Florian Fainelli]

On 5/2/2019 5:26 AM, Jonas Gorski wrote:
> Now that we have a driver for the clock controller, add nodes to allow
> devices to make use of it.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

Re: [PATCH 3/3] MIPS: BMIPS: add clock controller nodes

[Philippe Mathieu-Daudé]

On 5/2/19 2:26 PM, Jonas Gorski wrote:
> Now that we have a driver for the clock controller, add nodes to allow
> devices to make use of it.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH 3/3] MIPS: BMIPS: add clock controller nodes

[Paul Burton]

Hello,

Jonas Gorski wrote:
> Now that we have a driver for the clock controller, add nodes to allow
> devices to make use of it.
> 
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Applied to mips-next.

Thanks,
    Paul

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