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From: Oleksij Rempel <fishor@gmx.net>
To: Chuanhong Guo <gch981213@gmail.com>, Rob Herring <robh@kernel.org>
Cc: "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>,
	"open list:MIPS" <linux-mips@vger.kernel.org>,
	"open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Ralf Baechle <ralf@linux-mips.org>,
	Paul Burton <paul.burton@mips.com>,
	James Hogan <jhogan@kernel.org>, John Crispin <john@phrozen.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Weijie Gao <hackpascal@gmail.com>, NeilBrown <neil@brown.name>
Subject: Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation
Date: Sat, 17 Aug 2019 17:39:52 +0200	[thread overview]
Message-ID: <2d48f4a4-7d30-547b-21ee-6aadabe7d7c3@gmx.net> (raw)
In-Reply-To: <CAJsYDVKnf4M8jyVOyotRxs=SsHqjex_q60AwkX=QAPK33ivw-Q@mail.gmail.com>

Hi,

Am 17.08.19 um 16:42 schrieb Chuanhong Guo:
> Hi!
>
> On Tue, Aug 13, 2019 at 11:51 PM Rob Herring <robh@kernel.org> wrote:
>> [...]
>>> +Example:
>>> +     pll {
>>> +             compatible = "mediatek,mt7621-pll";
>>
>> You didn't answer Stephen's question on v1.
>
> I thought he was asking why there's a syscon in compatible string. I
> noticed that the syscon in my previous patch is a copy-paste error
> from elsewhere and dropped it.
>
>>
>> Based on this binding, there is no way to control/program the PLL. Is
>> this part of some IP block?
>
> The entire section is called "system control" in datasheet and is
> occupied in arch/mips/ralink/mt7621.c [0]
> Two clocks provided here is determined by reading some read-only
> registers in this part.
> There's another register in this section providing clock gates for
> every peripherals, but MTK doesn't provide a clock plan in their
> datasheet. I can't determine corresponding clock frequencies for every
> peripherals, thus unable to write a working clock driver.

In provided link [0] the  ralink_clk_init function is reading SYSC_REG_CPLL_CLKCFG0 R/W register.
This register is used to determine clock source,  clock freq and CPU or bus clocks.
SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks.
Jist wild assumption. All peripheral devices are suing bus clock.

IMO - this information is enough to create full blown drivers/clk/mediatek/clk-mt7621.c

>>> +
>>> +             #clock-cells = <1>;
>>> +             clock-output-names = "cpu", "bus";
>>> +     };
>>> --
>>> 2.21.0
>>>
>
> Regards,
> Chuanhong Guo
>
> [0] https://elixir.bootlin.com/linux/latest/source/arch/mips/ralink/mt7621.c#L156
>


  reply	other threads:[~2019-08-17 15:40 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-24  2:23 [PATCH v2 0/6] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 1/6] dt-bindings: clock: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 2/6] MIPS: ralink: drop ralink_clk_init for mt7621 Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 3/6] MIPS: ralink: add clock device providing cpu/bus clock " Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
2019-07-29 17:33   ` Paul Burton
2019-08-13 15:51   ` Rob Herring
2019-08-17 14:42     ` Chuanhong Guo
2019-08-17 15:39       ` Oleksij Rempel [this message]
2019-08-17 16:22         ` Chuanhong Guo
2019-08-17 18:05           ` Oleksij Rempel
2019-08-18  2:29             ` Chuanhong Guo
2019-08-18  6:10               ` Oleksij Rempel
2019-08-18  7:19                 ` Chuanhong Guo
2019-08-18  7:59                   ` Oleksij Rempel
2019-08-18  8:26                     ` Chuanhong Guo
2019-08-18  8:44                       ` Chuanhong Guo
2019-08-18  9:51                         ` Oleksij Rempel
2019-08-18 10:07                           ` Chuanhong Guo
2019-08-17 15:40       ` Oleksij Rempel
2019-07-24  2:23 ` [PATCH v2 5/6] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
2019-07-24  2:23 ` [PATCH v2 6/6] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo

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