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a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1596806733; bh=XfrD3CWWFnVEW2rWMOyI6dxR8hMqcjfEnhLHEp6qURk=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=SsBwpMHH3xr3zOmBKGCTkt3rncY+ySUuqNR42i2JBk6IJfabn0l895zpOCaMpUgEJ syzDx+kgHb5XXzUALvc+QoN/IpVsDoUBufsLtamJsjcse8IPCQUf1rG6hq8qohjB58 u9Ly2qEHZhXzTitWInNZrejlHC6EoabL/FY8KQjE= Subject: Re: [PATCH V3 1/2] MIPS: Loongson-3: Enable COP2 usage in kernel To: Thomas Bogendoerfer Cc: Huacai Chen , "open list:MIPS" , Fuxin Zhang , Zhangjin Wu References: <1588395344-5400-1-git-send-email-chenhc@lemote.com> <20200805121021.GA12598@alpha.franken.de> <1c3cb503-720f-059e-2bac-ae692203c389@flygoat.com> <20200807131357.GA11979@alpha.franken.de> From: Jiaxun Yang Message-ID: <410cf75c-4cf5-94d8-fbc9-821d38f8a299@flygoat.com> Date: Fri, 7 Aug 2020 21:25:25 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.1.0 MIME-Version: 1.0 In-Reply-To: <20200807131357.GA11979@alpha.franken.de> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: BD8AD425AB X-Spamd-Result: default: False [-0.10 / 10.00]; RCVD_VIA_SMTP_AUTH(0.00)[]; ARC_NA(0.00)[]; R_DKIM_ALLOW(0.00)[flygoat.com:s=default]; HFILTER_HELO_BAREIP(3.00)[213.133.102.83,1]; FROM_HAS_DN(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_GOOD(-0.10)[text/plain]; R_SPF_SOFTFAIL(0.00)[~all]; RCPT_COUNT_FIVE(0.00)[5]; ML_SERVERS(-3.10)[213.133.102.83]; TO_DN_ALL(0.00)[]; DKIM_TRACE(0.00)[flygoat.com:+]; RCVD_IN_DNSWL_NONE(0.00)[213.133.102.83:from]; DMARC_POLICY_ALLOW(0.00)[flygoat.com,none]; DMARC_POLICY_ALLOW_WITH_FAILURES(0.00)[]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:213.133.96.0/19, country:DE]; FREEMAIL_CC(0.00)[lemote.com,vger.kernel.org,gmail.com]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2] X-Rspamd-Server: mail20.mymailcheap.com Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org ÔÚ 2020/8/7 21:13, Thomas Bogendoerfer дµÀ: > On Wed, Aug 05, 2020 at 09:51:44PM +0800, Jiaxun Yang wrote: >>> yes there is. Since this COP2 is a total black box to me, it would be >>> really helpfull to get some docs for it or at least some information what >>> it exactly does and how you want to use it in kernel code. >> FYI: >> Loongson doesn't have any CU2 register. It just reused LWC2 & LDC2 opcode >> to define some load & store instructions (e.g. 128bit load to two GPRs). >> >> I have a collection of these instructions here[1]. >> >> From GS464E (3A2000+), execuating these instruction won't produce COP2 >> unusable >> exception. But older Loongson cores (GS464) will still produce COP2 >> exception, thus >> we should have CU2 enabled in kernel. That would allow us use to these >> instructions >> to optimize kernel. > thank you that makes things a little bit clearer. > > How will this be used in kernel code ? Special assembler routines or > by enabling gcc options ? Via special assembly routines, as -msoft-float will disable generation of these instructions in GCC. I knew Huacai have out-of-tree memcpy optimization and Xuerui have RAID5 optimiztion with these instructions. > >>> And finally what I stil don't like is the splittering of more >>> #ifdef LOONGSON into common code. I'd prefer a more generic way >>> to enable COPx for in kernel usage. Maybe a more generic config option >>> or a dynamic solution like the one for user land. >> Agreed. some Kconfig options or cpuinfo_mips.options can be helpful. > let's see whether this really is needed. > > To me it looks like the COP2 exception support for loongson makes > thing worse than it helps. How about the patch below ? There is still > a gap between starting the kernel and COP2 enabled for which I'm not > sure, if we are hitting COP2 instructions. Yes, the exception does not really make sense. What's your opinion Huacai? For in-kernel usage, we still have to enable it in genex. Thanks for your advice~ - Jiaxun > > Thomas. > > diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h > index 6b7396a6a115..dfa72e9be64a 100644 > --- a/arch/mips/include/asm/cop2.h > +++ b/arch/mips/include/asm/cop2.h > @@ -33,13 +33,6 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *); > #define cop2_present 1 > #define cop2_lazy_restore 0 > > -#elif defined(CONFIG_CPU_LOONGSON64) > - > -#define cop2_present 1 > -#define cop2_lazy_restore 1 > -#define cop2_save(r) do { (void)(r); } while (0) > -#define cop2_restore(r) do { (void)(r); } while (0) > - > #else > > #define cop2_present 0 > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index b95ef98fc847..f0a8ef5a8605 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -2194,6 +2194,11 @@ static void configure_status(void) > #ifdef CONFIG_64BIT > status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; > #endif > +#ifdef CONFIG_CPU_LOONGSON64 > + /* enable 16-bytes load/store instructions */ > + status_set |= ST0_CU2; > +#endif > + > if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) > status_set |= ST0_XX; > if (cpu_has_dsp) > > >