From: Florian Fainelli <f.fainelli@gmail.com>
To: Kamal Dasu <kdasu.kdev@gmail.com>,
linux-mips@vger.kernel.org,
bcm-kernel-feedback-list@broadcom.com
Cc: Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paulburton@kernel.org>,
James Hogan <jhogan@kernel.org>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhc@lemote.com>,
Mike Rapoport <rppt@linux.ibm.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
Date: Fri, 7 Feb 2020 14:35:40 -0800 [thread overview]
Message-ID: <44b41f44-b301-5268-93cb-e43f536e32c2@gmail.com> (raw)
In-Reply-To: <20200207223324.46011-1-kdasu.kdev@gmail.com>
On 2/7/20 2:33 PM, Kamal Dasu wrote:
> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> line can contain two instruction cache lines (64B), or four data cache
> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> secondary cache module (ZSCM) on DMA from device so that data returned is
> coherent during DMA read operations.
>
> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Thanks Kamal!
--
Florian
next prev parent reply other threads:[~2020-02-07 22:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-07 22:33 [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines Kamal Dasu
2020-02-07 22:35 ` Florian Fainelli [this message]
2020-03-11 20:54 ` Florian Fainelli
2020-03-11 21:44 ` Thomas Bogendoerfer
2020-03-13 3:09 ` Kamal Dasu
2020-03-16 15:31 ` Thomas Bogendoerfer
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