Linux-MIPS Archive on lore.kernel.org
 help / color / Atom feed
* Add Ingenic X1000 irqchip support.
@ 2019-01-26 15:38 Zhou Yanjie
  2019-01-26 15:38 ` [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
                   ` (5 more replies)
  0 siblings, 6 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-26 15:38 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

Add Ingenic X1000 irqchip support.



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
@ 2019-01-26 15:38 ` Zhou Yanjie
  2019-01-27 10:21   ` Marc Zyngier
  2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
  2019-01-26 15:38 ` [PATCH 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
                   ` (4 subsequent siblings)
  5 siblings, 2 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-26 15:38 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 49 ++++++++++++++++++++++---------------------
 1 file changed, 25 insertions(+), 24 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 2ff0898..2713ec4 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- *  JZ4740 platform IRQ support
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General	 Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
+ *  Ingenic XBurst platform IRQ support
  */
 
 #include <linux/errno.h>
@@ -19,6 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/ingenic.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -41,22 +33,35 @@ struct ingenic_intc_data {
 #define JZ_REG_INTC_PENDING	0x10
 #define CHIP_SIZE		0x20
 
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
 {
-	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-	uint32_t irq_reg;
+	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	bool have_irq = false;
+	u32 pending;
 	unsigned i;
 
+	chained_irq_enter(chip, desc);
 	for (i = 0; i < intc->num_chips; i++) {
-		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+		pending = readl(intc->base + (i * CHIP_SIZE) +
 				JZ_REG_INTC_PENDING);
-		if (!irq_reg)
+		if (!pending)
 			continue;
 
-		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+		have_irq = true;
+		while (pending) {
+			int bit = __ffs(pending);
+
+			generic_handle_irq(__fls(pending) + (i * 32) +
+					JZ4740_IRQ_BASE);
+			pending &= ~BIT(bit);
+		}
 	}
 
-	return IRQ_HANDLED;
+	if (!have_irq)
+		spurious_interrupt();
+
+	chained_irq_exit(chip, desc);
 }
 
 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -79,11 +84,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
 	intc_irq_set_mask(gc, gc->mask_cache);
 }
 
-static struct irqaction intc_cascade_action = {
-	.handler = intc_cascade,
-	.name = "SoC intc cascade interrupt",
-};
-
 static int __init ingenic_intc_of_init(struct device_node *node,
 				       unsigned num_chips)
 {
@@ -148,7 +148,8 @@ static int __init ingenic_intc_of_init(struct device_node *node,
 	if (!domain)
 		pr_warn("unable to register IRQ domain\n");
 
-	setup_irq(parent_irq, &intc_cascade_action);
+	irq_set_chained_handler_and_data(parent_irq,
+					ingenic_chained_handle_irq, intc);
 	return 0;
 
 out_unmap_irq:
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".
  2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
  2019-01-26 15:38 ` [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
@ 2019-01-26 15:38 ` Zhou Yanjie
  2019-01-26 15:38 ` [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-26 15:38 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 2713ec4..69be219 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -64,7 +64,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+						uint32_t mask)
 {
 	struct irq_chip_regs *regs = &gc->chip_types->regs;
 
@@ -75,13 +76,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
 void ingenic_intc_irq_suspend(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->wake_active);
+	ingenic_intc_irq_set_mask(gc, gc->wake_active);
 }
 
 void ingenic_intc_irq_resume(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->mask_cache);
+	ingenic_intc_irq_set_mask(gc, gc->mask_cache);
 }
 
 static int __init ingenic_intc_of_init(struct device_node *node,
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000.
  2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
  2019-01-26 15:38 ` [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
  2019-01-26 15:38 ` [PATCH 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
@ 2019-01-26 15:38 ` Zhou Yanjie
  2019-01-27 10:14   ` Marc Zyngier
  2019-01-26 15:38 ` [PATCH 4/4] " Zhou Yanjie
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-26 15:38 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with double precision hardware float point unit.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 69be219..0b643c7 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node *node,
 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 4/4] Irqchip: Ingenic: Add support for the X1000.
  2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
                   ` (2 preceding siblings ...)
  2019-01-26 15:38 ` [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
@ 2019-01-26 15:38 ` " Zhou Yanjie
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
  2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
  5 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-26 15:38 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with double precision hardware float point unit.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..fa69b3f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -8,6 +8,7 @@ Required properties:
     ingenic,jz4770-intc
     ingenic,jz4775-intc
     ingenic,jz4780-intc
+    ingenic,x1000-intc
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000.
  2019-01-26 15:38 ` [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
@ 2019-01-27 10:14   ` Marc Zyngier
  2019-01-27 14:51     ` Zhou Yanjie
  0 siblings, 1 reply; 35+ messages in thread
From: Marc Zyngier @ 2019-01-27 10:14 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton,
	mark.rutland, jason, tglx, syq, jiaxun.yang, 772753199

On Sat, 26 Jan 2019 15:38:42 +0000,
Zhou Yanjie <zhouyanjie@zoho.com> wrote:
> 
> Add support for probing the irq-ingenic driver on the X1000 Soc.
> X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
> with double precision hardware float point unit.

I don't think we need the marketing spiel, as none of the advertised
target market, ISA or feature set of this SoC is relevant for this
patch. Put it in the cover letter if you must.

Instead, explaining that it behaves just like any of the other "2chip"
Ingenic SoCs makes is much more relevant.

> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  drivers/irqchip/irq-ingenic.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
> index 69be219..0b643c7 100644
> --- a/drivers/irqchip/irq-ingenic.c
> +++ b/drivers/irqchip/irq-ingenic.c
> @@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node *node,
>  IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
>  IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
>  IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
> +IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
> -- 
> 2.7.4
> 
> 

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-01-26 15:38 ` [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
@ 2019-01-27 10:21   ` Marc Zyngier
  2019-01-27 14:49     ` Zhou Yanjie
  2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
  1 sibling, 1 reply; 35+ messages in thread
From: Marc Zyngier @ 2019-01-27 10:21 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton,
	mark.rutland, jason, tglx, syq, jiaxun.yang, 772753199

On Sat, 26 Jan 2019 15:38:40 +0000,
Zhou Yanjie <zhouyanjie@zoho.com> wrote:
> 
> The interrupt handling method is changed from old-style cascade to
> chained_irq which is more appropriate. Also, it can process the
> corner situation that more than one irq is coming to a single
> chip at the same time.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  drivers/irqchip/irq-ingenic.c | 49 ++++++++++++++++++++++---------------------
>  1 file changed, 25 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
> index 2ff0898..2713ec4 100644
> --- a/drivers/irqchip/irq-ingenic.c
> +++ b/drivers/irqchip/irq-ingenic.c
> @@ -1,16 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0
>  /*
>   *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
> - *  JZ4740 platform IRQ support
> - *
> - *  This program is free software; you can redistribute it and/or modify it
> - *  under  the terms of the GNU General	 Public License as published by the
> - *  Free Software Foundation;  either version 2 of the License, or (at your
> - *  option) any later version.
> - *
> - *  You should have received a copy of the GNU General Public License along
> - *  with this program; if not, write to the Free Software Foundation, Inc.,
> - *  675 Mass Ave, Cambridge, MA 02139, USA.
> - *
> + *  Ingenic XBurst platform IRQ support
>   */
>  
>  #include <linux/errno.h>
> @@ -19,6 +10,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/ioport.h>
>  #include <linux/irqchip.h>
> +#include <linux/irqchip/chained_irq.h>
>  #include <linux/irqchip/ingenic.h>
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
> @@ -41,22 +33,35 @@ struct ingenic_intc_data {
>  #define JZ_REG_INTC_PENDING	0x10
>  #define CHIP_SIZE		0x20
>  
> -static irqreturn_t intc_cascade(int irq, void *data)
> +static void ingenic_chained_handle_irq(struct irq_desc *desc)
>  {
> -	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
> -	uint32_t irq_reg;
> +	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	bool have_irq = false;
> +	u32 pending;
>  	unsigned i;
>  
> +	chained_irq_enter(chip, desc);
>  	for (i = 0; i < intc->num_chips; i++) {
> -		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
> +		pending = readl(intc->base + (i * CHIP_SIZE) +
>  				JZ_REG_INTC_PENDING);
> -		if (!irq_reg)
> +		if (!pending)
>  			continue;
>  
> -		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
> +		have_irq = true;
> +		while (pending) {
> +			int bit = __ffs(pending);

So 'bit' is the least significant bit in the pending word,

> +
> +			generic_handle_irq(__fls(pending) + (i * 32) +

and here you handle the *most significant* bit,

> +					JZ4740_IRQ_BASE);
> +			pending &= ~BIT(bit);

yet it is the least significant bit that you clear. I am tempted to
say that you have never tested this code with more than a single
interrupt.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-01-27 10:21   ` Marc Zyngier
@ 2019-01-27 14:49     ` Zhou Yanjie
  0 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-27 14:49 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton,
	mark.rutland, jason, tglx, syq, jiaxun.yang, 772753199

My fault, in the function "generic_handle_irq" should use "bit" instead 
of "__fls(irq_reg)".
It will be fixed in the v2.

On 2019年01月27日 18:21, Marc Zyngier wrote:
> On Sat, 26 Jan 2019 15:38:40 +0000,
> Zhou Yanjie <zhouyanjie@zoho.com> wrote:
>> The interrupt handling method is changed from old-style cascade to
>> chained_irq which is more appropriate. Also, it can process the
>> corner situation that more than one irq is coming to a single
>> chip at the same time.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>   drivers/irqchip/irq-ingenic.c | 49 ++++++++++++++++++++++---------------------
>>   1 file changed, 25 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
>> index 2ff0898..2713ec4 100644
>> --- a/drivers/irqchip/irq-ingenic.c
>> +++ b/drivers/irqchip/irq-ingenic.c
>> @@ -1,16 +1,7 @@
>> +// SPDX-License-Identifier: GPL-2.0
>>   /*
>>    *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
>> - *  JZ4740 platform IRQ support
>> - *
>> - *  This program is free software; you can redistribute it and/or modify it
>> - *  under  the terms of the GNU General	 Public License as published by the
>> - *  Free Software Foundation;  either version 2 of the License, or (at your
>> - *  option) any later version.
>> - *
>> - *  You should have received a copy of the GNU General Public License along
>> - *  with this program; if not, write to the Free Software Foundation, Inc.,
>> - *  675 Mass Ave, Cambridge, MA 02139, USA.
>> - *
>> + *  Ingenic XBurst platform IRQ support
>>    */
>>   
>>   #include <linux/errno.h>
>> @@ -19,6 +10,7 @@
>>   #include <linux/interrupt.h>
>>   #include <linux/ioport.h>
>>   #include <linux/irqchip.h>
>> +#include <linux/irqchip/chained_irq.h>
>>   #include <linux/irqchip/ingenic.h>
>>   #include <linux/of_address.h>
>>   #include <linux/of_irq.h>
>> @@ -41,22 +33,35 @@ struct ingenic_intc_data {
>>   #define JZ_REG_INTC_PENDING	0x10
>>   #define CHIP_SIZE		0x20
>>   
>> -static irqreturn_t intc_cascade(int irq, void *data)
>> +static void ingenic_chained_handle_irq(struct irq_desc *desc)
>>   {
>> -	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
>> -	uint32_t irq_reg;
>> +	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	bool have_irq = false;
>> +	u32 pending;
>>   	unsigned i;
>>   
>> +	chained_irq_enter(chip, desc);
>>   	for (i = 0; i < intc->num_chips; i++) {
>> -		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
>> +		pending = readl(intc->base + (i * CHIP_SIZE) +
>>   				JZ_REG_INTC_PENDING);
>> -		if (!irq_reg)
>> +		if (!pending)
>>   			continue;
>>   
>> -		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
>> +		have_irq = true;
>> +		while (pending) {
>> +			int bit = __ffs(pending);
> So 'bit' is the least significant bit in the pending word,
>
>> +
>> +			generic_handle_irq(__fls(pending) + (i * 32) +
> and here you handle the *most significant* bit,
>
>> +					JZ4740_IRQ_BASE);
>> +			pending &= ~BIT(bit);
> yet it is the least significant bit that you clear. I am tempted to
> say that you have never tested this code with more than a single
> interrupt.
>
> Thanks,
>
> 	M.
>




^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000.
  2019-01-27 10:14   ` Marc Zyngier
@ 2019-01-27 14:51     ` Zhou Yanjie
  0 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-27 14:51 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton,
	mark.rutland, jason, tglx, syq, jiaxun.yang, 772753199

Thanks for your suggestions, It will be deleted in the v2.

On 2019年01月27日 18:14, Marc Zyngier wrote:
> On Sat, 26 Jan 2019 15:38:42 +0000,
> Zhou Yanjie <zhouyanjie@zoho.com> wrote:
>> Add support for probing the irq-ingenic driver on the X1000 Soc.
>> X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
>> with double precision hardware float point unit.
> I don't think we need the marketing spiel, as none of the advertised
> target market, ISA or feature set of this SoC is relevant for this
> patch. Put it in the cover letter if you must.
>
> Instead, explaining that it behaves just like any of the other "2chip"
> Ingenic SoCs makes is much more relevant.
>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>   drivers/irqchip/irq-ingenic.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
>> index 69be219..0b643c7 100644
>> --- a/drivers/irqchip/irq-ingenic.c
>> +++ b/drivers/irqchip/irq-ingenic.c
>> @@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node *node,
>>   IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
>>   IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
>>   IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
>> +IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
>> -- 
>> 2.7.4
>>
>>
> Thanks,
>
> 	M.
>




^ permalink raw reply	[flat|nested] 35+ messages in thread

* Add Ingenic X1000 irqchip support v2.
  2019-01-26 15:38 ` [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
  2019-01-27 10:21   ` Marc Zyngier
@ 2019-01-27 15:50   ` Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
                       ` (3 more replies)
  1 sibling, 4 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-27 15:50 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

vi->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v2 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
@ 2019-01-27 15:50     ` Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
                       ` (2 subsequent siblings)
  3 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-27 15:50 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 48 +++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 2ff0898..5f775a1 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- *  JZ4740 platform IRQ support
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General	 Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
+ *  Ingenic XBurst platform IRQ support
  */
 
 #include <linux/errno.h>
@@ -19,6 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/ingenic.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -41,22 +33,34 @@ struct ingenic_intc_data {
 #define JZ_REG_INTC_PENDING	0x10
 #define CHIP_SIZE		0x20
 
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
 {
-	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-	uint32_t irq_reg;
+	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	bool have_irq = false;
+	uint32_t pending;
 	unsigned i;
 
+	chained_irq_enter(chip, desc);
 	for (i = 0; i < intc->num_chips; i++) {
-		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+		pending = readl(intc->base + (i * CHIP_SIZE) +
 				JZ_REG_INTC_PENDING);
-		if (!irq_reg)
+		if (!pending)
 			continue;
 
-		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+		have_irq = true;
+		while (pending) {
+			int bit = __fls(pending);
+
+			generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
+			pending &= ~BIT(bit);
+		}
 	}
 
-	return IRQ_HANDLED;
+	if (!have_irq)
+		spurious_interrupt();
+
+	chained_irq_exit(chip, desc);
 }
 
 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -79,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
 	intc_irq_set_mask(gc, gc->mask_cache);
 }
 
-static struct irqaction intc_cascade_action = {
-	.handler = intc_cascade,
-	.name = "SoC intc cascade interrupt",
-};
-
 static int __init ingenic_intc_of_init(struct device_node *node,
 				       unsigned num_chips)
 {
@@ -148,7 +147,8 @@ static int __init ingenic_intc_of_init(struct device_node *node,
 	if (!domain)
 		pr_warn("unable to register IRQ domain\n");
 
-	setup_irq(parent_irq, &intc_cascade_action);
+	irq_set_chained_handler_and_data(parent_irq,
+					ingenic_chained_handle_irq, intc);
 	return 0;
 
 out_unmap_irq:
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v2 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".
  2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
@ 2019-01-27 15:50     ` Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 4/4] " Zhou Yanjie
  3 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-27 15:50 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 5f775a1..32d090a 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -63,7 +63,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+						uint32_t mask)
 {
 	struct irq_chip_regs *regs = &gc->chip_types->regs;
 
@@ -74,13 +75,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
 void ingenic_intc_irq_suspend(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->wake_active);
+	ingenic_intc_irq_set_mask(gc, gc->wake_active);
 }
 
 void ingenic_intc_irq_resume(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->mask_cache);
+	ingenic_intc_irq_set_mask(gc, gc->mask_cache);
 }
 
 static int __init ingenic_intc_of_init(struct device_node *node,
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v2 3/4] Irqchip: Ingenic: Add support for the X1000.
  2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
@ 2019-01-27 15:50     ` Zhou Yanjie
  2019-01-27 15:50     ` [PATCH v2 4/4] " Zhou Yanjie
  3 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-27 15:50 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

Add support for probing the irq-ingenic driver on the X1000 Soc.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 32d090a..814c68c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -176,3 +176,4 @@ static int __init intc_2chip_of_init(struct device_node *node,
 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v2 4/4] Irqchip: Ingenic: Add support for the X1000.
  2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
                       ` (2 preceding siblings ...)
  2019-01-27 15:50     ` [PATCH v2 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
@ 2019-01-27 15:50     ` " Zhou Yanjie
  2019-01-30 19:43       ` Rob Herring
  3 siblings, 1 reply; 35+ messages in thread
From: Zhou Yanjie @ 2019-01-27 15:50 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, mark.rutland,
	marc.zyngier, jason, tglx, syq, jiaxun.yang, 772753199

Add support for probing the irq-ingenic driver on the X1000 Soc.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..fa69b3f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -8,6 +8,7 @@ Required properties:
     ingenic,jz4770-intc
     ingenic,jz4775-intc
     ingenic,jz4780-intc
+    ingenic,x1000-intc
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH v2 4/4] Irqchip: Ingenic: Add support for the X1000.
  2019-01-27 15:50     ` [PATCH v2 4/4] " Zhou Yanjie
@ 2019-01-30 19:43       ` Rob Herring
  0 siblings, 0 replies; 35+ messages in thread
From: Rob Herring @ 2019-01-30 19:43 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton,
	mark.rutland, marc.zyngier, jason, tglx, syq, jiaxun.yang,
	772753199

On Sun, 27 Jan 2019 23:50:32 +0800, Zhou Yanjie wrote:
> Add support for probing the irq-ingenic driver on the X1000 Soc.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3.
  2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
                   ` (3 preceding siblings ...)
  2019-01-26 15:38 ` [PATCH 4/4] " Zhou Yanjie
@ 2019-07-15 12:09 ` Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
                     ` (7 more replies)
  2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
  5 siblings, 8 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

v1->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".
v2->v3: Add support for probing irq-ingenic driver on JZ4760 and X1500 Soc.



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 2/8] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
                     ` (6 subsequent siblings)
  7 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 37 +++++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index f126255..49f7685 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- *  JZ4740 platform IRQ support
+ *  Ingenic XBurst platform IRQ support
  */
 
 #include <linux/errno.h>
@@ -10,6 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/ingenic.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -32,22 +33,34 @@ struct ingenic_intc_data {
 #define JZ_REG_INTC_PENDING	0x10
 #define CHIP_SIZE		0x20
 
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
 {
-	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-	uint32_t irq_reg;
+	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	bool have_irq = false;
+	uint32_t pending;
 	unsigned i;
 
+	chained_irq_enter(chip, desc);
 	for (i = 0; i < intc->num_chips; i++) {
-		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+		pending = readl(intc->base + (i * CHIP_SIZE) +
 				JZ_REG_INTC_PENDING);
-		if (!irq_reg)
+		if (!pending)
 			continue;
 
-		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+		have_irq = true;
+		while (pending) {
+			int bit = __fls(pending);
+
+			generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
+			pending &= ~BIT(bit);
+		}
 	}
 
-	return IRQ_HANDLED;
+	if (!have_irq)
+		spurious_interrupt();
+
+	chained_irq_exit(chip, desc);
 }
 
 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -70,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
 	intc_irq_set_mask(gc, gc->mask_cache);
 }
 
-static struct irqaction intc_cascade_action = {
-	.handler = intc_cascade,
-	.name = "SoC intc cascade interrupt",
-};
-
 static int __init ingenic_intc_of_init(struct device_node *node,
 				       unsigned num_chips)
 {
@@ -139,7 +147,8 @@ static int __init ingenic_intc_of_init(struct device_node *node,
 	if (!domain)
 		pr_warn("unable to register IRQ domain\n");
 
-	setup_irq(parent_irq, &intc_cascade_action);
+	irq_set_chained_handler_and_data(parent_irq,
+					ingenic_chained_handle_irq, intc);
 	return 0;
 
 out_unmap_irq:
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 2/8] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings Zhou Yanjie
                     ` (5 subsequent siblings)
  7 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 49f7685..8430f5a 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -63,7 +63,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+						uint32_t mask)
 {
 	struct irq_chip_regs *regs = &gc->chip_types->regs;
 
@@ -74,13 +75,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
 void ingenic_intc_irq_suspend(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->wake_active);
+	ingenic_intc_irq_set_mask(gc, gc->wake_active);
 }
 
 void ingenic_intc_irq_resume(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->mask_cache);
+	ingenic_intc_irq_set_mask(gc, gc->mask_cache);
 }
 
 static int __init ingenic_intc_of_init(struct device_node *node,
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings.
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 2/8] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  2019-07-26 13:36     ` Marc Zyngier
  2019-07-15 12:09   ` [PATCH v3 4/8] irqchip: Ingenic: Add support for JZ4760 and JZ4760B Zhou Yanjie
                     ` (4 subsequent siblings)
  7 siblings, 1 reply; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

Add the interrupt-controller bindings for the JZ4760 Soc and
the JZ4760B Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..fa1ad54 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -5,6 +5,8 @@ Required properties:
 - compatible : should be "ingenic,<socname>-intc". Valid strings are:
     ingenic,jz4740-intc
     ingenic,jz4725b-intc
+    ingenic,jz4760-intc
+    ingenic,jz4760b-intc
     ingenic,jz4770-intc
     ingenic,jz4775-intc
     ingenic,jz4780-intc
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 4/8] irqchip: Ingenic: Add support for JZ4760 and JZ4760B.
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
                     ` (2 preceding siblings ...)
  2019-07-15 12:09   ` [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 5/8] dt-bindings: interrupt-controller: Add X1000 and X1000E bindings Zhou Yanjie
                     ` (3 subsequent siblings)
  7 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

Add support for probing the irq-ingenic driver on the JZ4760 Soc
and the JZ4760B Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 8430f5a..e9e959c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -173,6 +173,8 @@ static int __init intc_2chip_of_init(struct device_node *node,
 {
 	return ingenic_intc_of_init(node, 2);
 }
+IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 5/8] dt-bindings: interrupt-controller: Add X1000 and X1000E bindings.
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
                     ` (3 preceding siblings ...)
  2019-07-15 12:09   ` [PATCH v3 4/8] irqchip: Ingenic: Add support for JZ4760 and JZ4760B Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 6/8] irqchip: Ingenic: Add support for X1000 and X1000E Zhou Yanjie
                     ` (2 subsequent siblings)
  7 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

Add the interrupt-controller bindings for the X1000 Soc and
the X1000E Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index fa1ad54..4f91bda 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -10,6 +10,8 @@ Required properties:
     ingenic,jz4770-intc
     ingenic,jz4775-intc
     ingenic,jz4780-intc
+    ingenic,x1000-intc
+    ingenic,x1000e-intc
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 6/8] irqchip: Ingenic: Add support for X1000 and X1000E.
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
                     ` (4 preceding siblings ...)
  2019-07-15 12:09   ` [PATCH v3 5/8] dt-bindings: interrupt-controller: Add X1000 and X1000E bindings Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 7/8] dt-bindings: interrupt-controller: Add X1500 bindings Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 8/8] irqchip: Ingenic: Add support for X1500 Zhou Yanjie
  7 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

Add support for probing the irq-ingenic driver on the X1000 Soc
and the X1000E Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index e9e959c..e8f7ae7 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -178,3 +178,5 @@ IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", intc_2chip_of_init);
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 7/8] dt-bindings: interrupt-controller: Add X1500 bindings.
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
                     ` (5 preceding siblings ...)
  2019-07-15 12:09   ` [PATCH v3 6/8] irqchip: Ingenic: Add support for X1000 and X1000E Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  2019-07-15 12:09   ` [PATCH v3 8/8] irqchip: Ingenic: Add support for X1500 Zhou Yanjie
  7 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

Add the interrupt-controller bindings for the
X1500 Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index 4f91bda..a96e120 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -12,6 +12,7 @@ Required properties:
     ingenic,jz4780-intc
     ingenic,x1000-intc
     ingenic,x1000e-intc
+    ingenic,x1500-intc
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH v3 8/8] irqchip: Ingenic: Add support for X1500.
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
                     ` (6 preceding siblings ...)
  2019-07-15 12:09   ` [PATCH v3 7/8] dt-bindings: interrupt-controller: Add X1500 bindings Zhou Yanjie
@ 2019-07-15 12:09   ` Zhou Yanjie
  7 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason, marc.zyngier

Add support for probing the irq-ingenic driver on the
X1500 Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index e8f7ae7..b72430c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -180,3 +180,4 @@ IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1500_intc, "ingenic,x1500-intc", intc_2chip_of_init);
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings.
  2019-07-15 12:09   ` [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings Zhou Yanjie
@ 2019-07-26 13:36     ` Marc Zyngier
  2019-07-28 17:39       ` Zhou Yanjie
  0 siblings, 1 reply; 35+ messages in thread
From: Marc Zyngier @ 2019-07-26 13:36 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason

On Mon, 15 Jul 2019 13:09:50 +0100,
Zhou Yanjie <zhouyanjie@zoho.com> wrote:
> 
> Add the interrupt-controller bindings for the JZ4760 Soc and
> the JZ4760B Soc from Ingenic.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
> index d4373d0..fa1ad54 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
> @@ -5,6 +5,8 @@ Required properties:
>  - compatible : should be "ingenic,<socname>-intc". Valid strings are:
>      ingenic,jz4740-intc
>      ingenic,jz4725b-intc
> +    ingenic,jz4760-intc
> +    ingenic,jz4760b-intc
>      ingenic,jz4770-intc
>      ingenic,jz4775-intc
>      ingenic,jz4780-intc
> -- 
> 2.7.4
> 
> 

This should be combined with patches 5 and 7. I don't see the need for
multiple patches. Same thing should happen with patches 4, 6 and 8.

Thanks,

	M.

-- 
Jazz is not dead, it just smells funny.

^ permalink raw reply	[flat|nested] 35+ messages in thread

* Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4.
  2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
                   ` (4 preceding siblings ...)
  2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
@ 2019-07-28 17:34 ` Zhou Yanjie
  2019-07-28 17:34   ` [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
                     ` (3 more replies)
  5 siblings, 4 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

v1->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".
v2->v3: Add support for probing irq-ingenic driver on JZ4760 and X1500 Soc.
v3->v4: Combined with patches 5 and 7, combined with patches 4, 6 and 8.



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
@ 2019-07-28 17:34   ` Zhou Yanjie
  2019-07-29 17:19     ` Paul Cercueil
  2019-07-28 17:34   ` [PATCH 2/4 v4] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
                     ` (2 subsequent siblings)
  3 siblings, 1 reply; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 37 +++++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index f126255..49f7685 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- *  JZ4740 platform IRQ support
+ *  Ingenic XBurst platform IRQ support
  */
 
 #include <linux/errno.h>
@@ -10,6 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/ingenic.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -32,22 +33,34 @@ struct ingenic_intc_data {
 #define JZ_REG_INTC_PENDING	0x10
 #define CHIP_SIZE		0x20
 
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
 {
-	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-	uint32_t irq_reg;
+	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	bool have_irq = false;
+	uint32_t pending;
 	unsigned i;
 
+	chained_irq_enter(chip, desc);
 	for (i = 0; i < intc->num_chips; i++) {
-		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+		pending = readl(intc->base + (i * CHIP_SIZE) +
 				JZ_REG_INTC_PENDING);
-		if (!irq_reg)
+		if (!pending)
 			continue;
 
-		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+		have_irq = true;
+		while (pending) {
+			int bit = __fls(pending);
+
+			generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
+			pending &= ~BIT(bit);
+		}
 	}
 
-	return IRQ_HANDLED;
+	if (!have_irq)
+		spurious_interrupt();
+
+	chained_irq_exit(chip, desc);
 }
 
 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -70,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
 	intc_irq_set_mask(gc, gc->mask_cache);
 }
 
-static struct irqaction intc_cascade_action = {
-	.handler = intc_cascade,
-	.name = "SoC intc cascade interrupt",
-};
-
 static int __init ingenic_intc_of_init(struct device_node *node,
 				       unsigned num_chips)
 {
@@ -139,7 +147,8 @@ static int __init ingenic_intc_of_init(struct device_node *node,
 	if (!domain)
 		pr_warn("unable to register IRQ domain\n");
 
-	setup_irq(parent_irq, &intc_cascade_action);
+	irq_set_chained_handler_and_data(parent_irq,
+					ingenic_chained_handle_irq, intc);
 	return 0;
 
 out_unmap_irq:
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 2/4 v4] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".
  2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
  2019-07-28 17:34   ` [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
@ 2019-07-28 17:34   ` Zhou Yanjie
  2019-07-28 17:34   ` [PATCH 3/4 v4] dt-bindings: interrupt-controller: Add new Ingenic Socs bindings Zhou Yanjie
  2019-07-28 17:34   ` [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs Zhou Yanjie
  3 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 49f7685..8430f5a 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -63,7 +63,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+						uint32_t mask)
 {
 	struct irq_chip_regs *regs = &gc->chip_types->regs;
 
@@ -74,13 +75,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
 void ingenic_intc_irq_suspend(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->wake_active);
+	ingenic_intc_irq_set_mask(gc, gc->wake_active);
 }
 
 void ingenic_intc_irq_resume(struct irq_data *data)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-	intc_irq_set_mask(gc, gc->mask_cache);
+	ingenic_intc_irq_set_mask(gc, gc->mask_cache);
 }
 
 static int __init ingenic_intc_of_init(struct device_node *node,
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 3/4 v4] dt-bindings: interrupt-controller: Add new Ingenic Socs bindings.
  2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
  2019-07-28 17:34   ` [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
  2019-07-28 17:34   ` [PATCH 2/4 v4] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
@ 2019-07-28 17:34   ` Zhou Yanjie
  2019-07-28 17:34   ` [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs Zhou Yanjie
  3 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

Add the interrupt-controller bindings for the JZ4760/JZ4760B and
the X1000/X1000E and the X1500 Socs from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 .../devicetree/bindings/interrupt-controller/ingenic,intc.txt        | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..a96e120 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -5,9 +5,14 @@ Required properties:
 - compatible : should be "ingenic,<socname>-intc". Valid strings are:
     ingenic,jz4740-intc
     ingenic,jz4725b-intc
+    ingenic,jz4760-intc
+    ingenic,jz4760b-intc
     ingenic,jz4770-intc
     ingenic,jz4775-intc
     ingenic,jz4780-intc
+    ingenic,x1000-intc
+    ingenic,x1000e-intc
+    ingenic,x1500-intc
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs.
  2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
                     ` (2 preceding siblings ...)
  2019-07-28 17:34   ` [PATCH 3/4 v4] dt-bindings: interrupt-controller: Add new Ingenic Socs bindings Zhou Yanjie
@ 2019-07-28 17:34   ` Zhou Yanjie
  2019-07-29 17:25     ` Paul Cercueil
  3 siblings, 1 reply; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
  To: linux-mips
  Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

Add support for probing the irq-ingenic driver on the JZ4760/JZ4760B
and the X1000/X1000E and the X1500 Socs from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/irqchip/irq-ingenic.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 8430f5a..b72430c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -173,6 +173,11 @@ static int __init intc_2chip_of_init(struct device_node *node,
 {
 	return ingenic_intc_of_init(node, 2);
 }
+IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1500_intc, "ingenic,x1500-intc", intc_2chip_of_init);
-- 
2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings.
  2019-07-26 13:36     ` Marc Zyngier
@ 2019-07-28 17:39       ` Zhou Yanjie
  0 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-28 17:39 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: linux-mips, linux-kernel, devicetree, paul.burton, tglx, robh+dt,
	mark.rutland, jason

Hi Marc,

These patches has been combined in v4.

Thanks

On 2019年07月26日 21:36, Marc Zyngier wrote:
> On Mon, 15 Jul 2019 13:09:50 +0100,
> Zhou Yanjie <zhouyanjie@zoho.com> wrote:
>> Add the interrupt-controller bindings for the JZ4760 Soc and
>> the JZ4760B Soc from Ingenic.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>   Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>> index d4373d0..fa1ad54 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>> @@ -5,6 +5,8 @@ Required properties:
>>   - compatible : should be "ingenic,<socname>-intc". Valid strings are:
>>       ingenic,jz4740-intc
>>       ingenic,jz4725b-intc
>> +    ingenic,jz4760-intc
>> +    ingenic,jz4760b-intc
>>       ingenic,jz4770-intc
>>       ingenic,jz4775-intc
>>       ingenic,jz4780-intc
>> -- 
>> 2.7.4
>>
>>
> This should be combined with patches 5 and 7. I don't see the need for
> multiple patches. Same thing should happen with patches 4, 6 and 8.
>
> Thanks,
>
> 	M.
>




^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-07-28 17:34   ` [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
@ 2019-07-29 17:19     ` Paul Cercueil
  2019-07-30  6:41       ` Zhou Yanjie
  0 siblings, 1 reply; 35+ messages in thread
From: Paul Cercueil @ 2019-07-29 17:19 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

Hi Zhou,



Le dim. 28 juil. 2019 à 13:34, Zhou Yanjie <zhouyanjie@zoho.com> a 
écrit :
> The interrupt handling method is changed from old-style cascade to
> chained_irq which is more appropriate. Also, it can process the
> corner situation that more than one irq is coming to a single
> chip at the same time.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  drivers/irqchip/irq-ingenic.c | 37 
> +++++++++++++++++++++++--------------
>  1 file changed, 23 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-ingenic.c 
> b/drivers/irqchip/irq-ingenic.c
> index f126255..49f7685 100644
> --- a/drivers/irqchip/irq-ingenic.c
> +++ b/drivers/irqchip/irq-ingenic.c
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-or-later
>  /*
>   *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
> - *  JZ4740 platform IRQ support
> + *  Ingenic XBurst platform IRQ support
>   */
> 
>  #include <linux/errno.h>
> @@ -10,6 +10,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/ioport.h>
>  #include <linux/irqchip.h>
> +#include <linux/irqchip/chained_irq.h>
>  #include <linux/irqchip/ingenic.h>
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
> @@ -32,22 +33,34 @@ struct ingenic_intc_data {
>  #define JZ_REG_INTC_PENDING	0x10
>  #define CHIP_SIZE		0x20
> 
> -static irqreturn_t intc_cascade(int irq, void *data)
> +static void ingenic_chained_handle_irq(struct irq_desc *desc)
>  {
> -	struct ingenic_intc_data *intc = irq_get_handler_data(irq);
> -	uint32_t irq_reg;
> +	struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	bool have_irq = false;
> +	uint32_t pending;
>  	unsigned i;
> 
> +	chained_irq_enter(chip, desc);
>  	for (i = 0; i < intc->num_chips; i++) {
> -		irq_reg = readl(intc->base + (i * CHIP_SIZE) +
> +		pending = readl(intc->base + (i * CHIP_SIZE) +
>  				JZ_REG_INTC_PENDING);
> -		if (!irq_reg)
> +		if (!pending)
>  			continue;
> 
> -		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
> +		have_irq = true;
> +		while (pending) {
> +			int bit = __fls(pending);

Use the for_each_set_bit() macro here, that will be simpler.


> +
> +			generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
> +			pending &= ~BIT(bit);
> +		}
>  	}
> 
> -	return IRQ_HANDLED;
> +	if (!have_irq)
> +		spurious_interrupt();
> +
> +	chained_irq_exit(chip, desc);
>  }
> 
>  static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t 
> mask)
> @@ -70,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
>  	intc_irq_set_mask(gc, gc->mask_cache);
>  }
> 
> -static struct irqaction intc_cascade_action = {
> -	.handler = intc_cascade,
> -	.name = "SoC intc cascade interrupt",
> -};
> -
>  static int __init ingenic_intc_of_init(struct device_node *node,
>  				       unsigned num_chips)
>  {
> @@ -139,7 +147,8 @@ static int __init ingenic_intc_of_init(struct 
> device_node *node,
>  	if (!domain)
>  		pr_warn("unable to register IRQ domain\n");
> 
> -	setup_irq(parent_irq, &intc_cascade_action);
> +	irq_set_chained_handler_and_data(parent_irq,
> +					ingenic_chained_handle_irq, intc);
>  	return 0;
> 
>  out_unmap_irq:
> --
> 2.7.4



^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs.
  2019-07-28 17:34   ` [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs Zhou Yanjie
@ 2019-07-29 17:25     ` Paul Cercueil
  2019-07-30  6:26       ` Zhou Yanjie
  0 siblings, 1 reply; 35+ messages in thread
From: Paul Cercueil @ 2019-07-29 17:25 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier



Le dim. 28 juil. 2019 à 13:34, Zhou Yanjie <zhouyanjie@zoho.com> a 
écrit :
> Add support for probing the irq-ingenic driver on the JZ4760/JZ4760B
> and the X1000/X1000E and the X1500 Socs from Ingenic.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>  drivers/irqchip/irq-ingenic.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-ingenic.c 
> b/drivers/irqchip/irq-ingenic.c
> index 8430f5a..b72430c 100644
> --- a/drivers/irqchip/irq-ingenic.c
> +++ b/drivers/irqchip/irq-ingenic.c
> @@ -173,6 +173,11 @@ static int __init intc_2chip_of_init(struct 
> device_node *node,
>  {
>  	return ingenic_intc_of_init(node, 2);
>  }
> +IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", 
> intc_2chip_of_init);
> +IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", 
> intc_2chip_of_init);
>  IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", 
> intc_2chip_of_init);
>  IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", 
> intc_2chip_of_init);
>  IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", 
> intc_2chip_of_init);
> +IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", 
> intc_2chip_of_init);
> +IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", 
> intc_2chip_of_init);
> +IRQCHIP_DECLARE(x1500_intc, "ingenic,x1500-intc", 
> intc_2chip_of_init);

All these compatible strings point to the exact same behaviour. It was
already a mistake to have the three "ingenic,jz47[70,75,80]-intc" here;
there should have been only one, e.g. "ingenic,jz4770-intc" and the 
other
two SoCs using it as a fallback compatible.

I think you don't need to add these, and in your devicetree just use
"ingenic,jz4780-intc" as a fallback compatible.

Cheers,
-Paul



^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs.
  2019-07-29 17:25     ` Paul Cercueil
@ 2019-07-30  6:26       ` Zhou Yanjie
  0 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-30  6:26 UTC (permalink / raw)
  To: Paul Cercueil
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

Hi Paul,
It seems very strange to appear another soc model in one soc's devicetree,
and before submitting this patch I referred to some other irq drivers. 
Similar
usage was found in irq-sunxi-nmi.c and irq-omap-intc.c, and the original
irq-ingenic.c was declare jz4770, jz4775, jz4780 in the same way. So I 
followed
the same method to add the declare of jz4760/x1000/x1500, this may be a 
little
better.

On 2019年07月30日 01:25, Paul Cercueil wrote:
>
>
> Le dim. 28 juil. 2019 à 13:34, Zhou Yanjie <zhouyanjie@zoho.com> a 
> écrit :
>> Add support for probing the irq-ingenic driver on the JZ4760/JZ4760B
>> and the X1000/X1000E and the X1500 Socs from Ingenic.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>  drivers/irqchip/irq-ingenic.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-ingenic.c 
>> b/drivers/irqchip/irq-ingenic.c
>> index 8430f5a..b72430c 100644
>> --- a/drivers/irqchip/irq-ingenic.c
>> +++ b/drivers/irqchip/irq-ingenic.c
>> @@ -173,6 +173,11 @@ static int __init intc_2chip_of_init(struct 
>> device_node *node,
>>  {
>>      return ingenic_intc_of_init(node, 2);
>>  }
>> +IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", 
>> intc_2chip_of_init);
>> +IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", 
>> intc_2chip_of_init);
>>  IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", 
>> intc_2chip_of_init);
>>  IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", 
>> intc_2chip_of_init);
>>  IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", 
>> intc_2chip_of_init);
>> +IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
>> +IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", 
>> intc_2chip_of_init);
>> +IRQCHIP_DECLARE(x1500_intc, "ingenic,x1500-intc", intc_2chip_of_init);
>
> All these compatible strings point to the exact same behaviour. It was
> already a mistake to have the three "ingenic,jz47[70,75,80]-intc" here;
> there should have been only one, e.g. "ingenic,jz4770-intc" and the other
> two SoCs using it as a fallback compatible.
>
> I think you don't need to add these, and in your devicetree just use
> "ingenic,jz4780-intc" as a fallback compatible.
>
> Cheers,
> -Paul
>
>




^ permalink raw reply	[flat|nested] 35+ messages in thread

* Re: [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
  2019-07-29 17:19     ` Paul Cercueil
@ 2019-07-30  6:41       ` Zhou Yanjie
  0 siblings, 0 replies; 35+ messages in thread
From: Zhou Yanjie @ 2019-07-30  6:41 UTC (permalink / raw)
  To: Paul Cercueil
  Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton, tglx,
	mark.rutland, jason, marc.zyngier

Hi Paul,
Thanks for your suggestion, and after receiving Marc's comments,
if this patch can be continued, I'll use for_each_set_bit() to simplify
code in v5.

On 2019年07月30日 01:19, Paul Cercueil wrote:
> Hi Zhou,
>
>
>
> Le dim. 28 juil. 2019 à 13:34, Zhou Yanjie <zhouyanjie@zoho.com> a 
> écrit :
>> The interrupt handling method is changed from old-style cascade to
>> chained_irq which is more appropriate. Also, it can process the
>> corner situation that more than one irq is coming to a single
>> chip at the same time.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>  drivers/irqchip/irq-ingenic.c | 37 
>> +++++++++++++++++++++++--------------
>>  1 file changed, 23 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-ingenic.c 
>> b/drivers/irqchip/irq-ingenic.c
>> index f126255..49f7685 100644
>> --- a/drivers/irqchip/irq-ingenic.c
>> +++ b/drivers/irqchip/irq-ingenic.c
>> @@ -1,7 +1,7 @@
>>  // SPDX-License-Identifier: GPL-2.0-or-later
>>  /*
>>   *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
>> - *  JZ4740 platform IRQ support
>> + *  Ingenic XBurst platform IRQ support
>>   */
>>
>>  #include <linux/errno.h>
>> @@ -10,6 +10,7 @@
>>  #include <linux/interrupt.h>
>>  #include <linux/ioport.h>
>>  #include <linux/irqchip.h>
>> +#include <linux/irqchip/chained_irq.h>
>>  #include <linux/irqchip/ingenic.h>
>>  #include <linux/of_address.h>
>>  #include <linux/of_irq.h>
>> @@ -32,22 +33,34 @@ struct ingenic_intc_data {
>>  #define JZ_REG_INTC_PENDING    0x10
>>  #define CHIP_SIZE        0x20
>>
>> -static irqreturn_t intc_cascade(int irq, void *data)
>> +static void ingenic_chained_handle_irq(struct irq_desc *desc)
>>  {
>> -    struct ingenic_intc_data *intc = irq_get_handler_data(irq);
>> -    uint32_t irq_reg;
>> +    struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
>> +    struct irq_chip *chip = irq_desc_get_chip(desc);
>> +    bool have_irq = false;
>> +    uint32_t pending;
>>      unsigned i;
>>
>> +    chained_irq_enter(chip, desc);
>>      for (i = 0; i < intc->num_chips; i++) {
>> -        irq_reg = readl(intc->base + (i * CHIP_SIZE) +
>> +        pending = readl(intc->base + (i * CHIP_SIZE) +
>>                  JZ_REG_INTC_PENDING);
>> -        if (!irq_reg)
>> +        if (!pending)
>>              continue;
>>
>> -        generic_handle_irq(__fls(irq_reg) + (i * 32) + 
>> JZ4740_IRQ_BASE);
>> +        have_irq = true;
>> +        while (pending) {
>> +            int bit = __fls(pending);
>
> Use the for_each_set_bit() macro here, that will be simpler.
>
>
>> +
>> +            generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
>> +            pending &= ~BIT(bit);
>> +        }
>>      }
>>
>> -    return IRQ_HANDLED;
>> +    if (!have_irq)
>> +        spurious_interrupt();
>> +
>> +    chained_irq_exit(chip, desc);
>>  }
>>
>>  static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t 
>> mask)
>> @@ -70,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
>>      intc_irq_set_mask(gc, gc->mask_cache);
>>  }
>>
>> -static struct irqaction intc_cascade_action = {
>> -    .handler = intc_cascade,
>> -    .name = "SoC intc cascade interrupt",
>> -};
>> -
>>  static int __init ingenic_intc_of_init(struct device_node *node,
>>                         unsigned num_chips)
>>  {
>> @@ -139,7 +147,8 @@ static int __init ingenic_intc_of_init(struct 
>> device_node *node,
>>      if (!domain)
>>          pr_warn("unable to register IRQ domain\n");
>>
>> -    setup_irq(parent_irq, &intc_cascade_action);
>> +    irq_set_chained_handler_and_data(parent_irq,
>> +                    ingenic_chained_handle_irq, intc);
>>      return 0;
>>
>>  out_unmap_irq:
>> -- 
>> 2.7.4
>
>




^ permalink raw reply	[flat|nested] 35+ messages in thread

end of thread, back to index

Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-26 15:38 Add Ingenic X1000 irqchip support Zhou Yanjie
2019-01-26 15:38 ` [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-01-27 10:21   ` Marc Zyngier
2019-01-27 14:49     ` Zhou Yanjie
2019-01-27 15:50   ` Add Ingenic X1000 irqchip support v2 Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
2019-01-27 15:50     ` [PATCH v2 4/4] " Zhou Yanjie
2019-01-30 19:43       ` Rob Herring
2019-01-26 15:38 ` [PATCH 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-01-26 15:38 ` [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000 Zhou Yanjie
2019-01-27 10:14   ` Marc Zyngier
2019-01-27 14:51     ` Zhou Yanjie
2019-01-26 15:38 ` [PATCH 4/4] " Zhou Yanjie
2019-07-15 12:09 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3 Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 2/8] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings Zhou Yanjie
2019-07-26 13:36     ` Marc Zyngier
2019-07-28 17:39       ` Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 4/8] irqchip: Ingenic: Add support for JZ4760 and JZ4760B Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 5/8] dt-bindings: interrupt-controller: Add X1000 and X1000E bindings Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 6/8] irqchip: Ingenic: Add support for X1000 and X1000E Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 7/8] dt-bindings: interrupt-controller: Add X1500 bindings Zhou Yanjie
2019-07-15 12:09   ` [PATCH v3 8/8] irqchip: Ingenic: Add support for X1500 Zhou Yanjie
2019-07-28 17:34 ` Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4 Zhou Yanjie
2019-07-28 17:34   ` [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq Zhou Yanjie
2019-07-29 17:19     ` Paul Cercueil
2019-07-30  6:41       ` Zhou Yanjie
2019-07-28 17:34   ` [PATCH 2/4 v4] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_" Zhou Yanjie
2019-07-28 17:34   ` [PATCH 3/4 v4] dt-bindings: interrupt-controller: Add new Ingenic Socs bindings Zhou Yanjie
2019-07-28 17:34   ` [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs Zhou Yanjie
2019-07-29 17:25     ` Paul Cercueil
2019-07-30  6:26       ` Zhou Yanjie

Linux-MIPS Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-mips/0 linux-mips/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-mips linux-mips/ https://lore.kernel.org/linux-mips \
		linux-mips@vger.kernel.org linux-mips@archiver.kernel.org
	public-inbox-index linux-mips


Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-mips


AGPL code for this site: git clone https://public-inbox.org/ public-inbox