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From: Zhou Yanjie <zhouyanjie@zoho.com>
To: Paul Cercueil <paul@crapouillou.net>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, robh+dt@kernel.org,
	paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org,
	mripard@kernel.org, shawnguo@kernel.org, mark.rutland@arm.com,
	syq@debian.org, ralf@linux-mips.org, heiko@sntech.de,
	icenowy@aosc.io, laurent.pinchart@ideasonboard.com,
	krzk@kernel.org, geert+renesas@glider.be,
	prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com,
	zhenwenjin@gmail.com
Subject: Re: [PATCH 1/4] MIPS: Ingenic: initial X1000 support.
Date: Fri, 22 Nov 2019 23:10:15 +0800	[thread overview]
Message-ID: <5DD7FA57.7070209@zoho.com> (raw)
In-Reply-To: <1574433409.3.0@crapouillou.net>

Hi Paul,

On 2019年11月22日 22:36, Paul Cercueil wrote:
> Hi Zhou,
>
>
> Le ven., nov. 22, 2019 at 21:11, Zhou Yanjie <zhouyanjie@zoho.com> a 
> écrit :
>> Support the Ingenic X1000 SoC using the code under arch/mips/jz4740.
>> This is left unselectable in Kconfig until a X1000 based board is
>> added in a later commit.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>  arch/mips/boot/dts/ingenic/x1000.dtsi | 161 
>> ++++++++++++++++++++++++++++++++++
>>  arch/mips/jz4740/Kconfig              |   6 ++
>>  arch/mips/jz4740/time.c               |   4 +-
>>  3 files changed, 170 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
>>
>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi 
>> b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> new file mode 100644
>> index 0000000..b8658a6
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> @@ -0,0 +1,161 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +#include <dt-bindings/clock/x1000-cgu.h>
>> +
>> +/ {
>> +    #address-cells = <1>;
>> +    #size-cells = <1>;
>> +    compatible = "ingenic,x1000", "ingenic,x1000e";
>> +
>> +    cpuintc: interrupt-controller {
>> +        #address-cells = <0>;
>> +        #interrupt-cells = <1>;
>> +        interrupt-controller;
>> +        compatible = "mti,cpu-interrupt-controller";
>> +    };
>> +
>> +    intc: interrupt-controller@10001000 {
>> +        compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
>> +        reg = <0x10001000 0x50>;
>> +
>> +        interrupt-controller;
>> +        #interrupt-cells = <1>;
>> +
>> +        interrupt-parent = <&cpuintc>;
>> +        interrupts = <2>;
>> +    };
>> +
>> +    exclk: ext {
>> +        compatible = "fixed-clock";
>> +        #clock-cells = <0>;
>> +    };
>> +
>> +    rtclk: rtc {
>> +        compatible = "fixed-clock";
>> +        #clock-cells = <0>;
>> +        clock-frequency = <32768>;
>> +    };
>> +
>> +    cgu: x1000-cgu@10000000 {
>> +        compatible = "ingenic,x1000-cgu";
>> +        reg = <0x10000000 0x100>;
>> +
>> +        clocks = <&exclk>, <&rtclk>;
>> +        clock-names = "ext", "rtc";
>> +
>> +        #clock-cells = <1>;
>> +    };
>> +
>> +    apb {
>> +        compatible = "simple-bus";
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
>> +        ranges = <>;
>> +
>> +        uart0: serial@10030000 {
>> +            compatible = "ingenic,x1000-uart";
>> +            reg = <0x10030000 0x100>;
>> +
>> +            interrupt-parent = <&intc>;
>> +            interrupts = <51>;
>> +
>> +            clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
>> +            clock-names = "baud", "module";
>> +
>> +            status = "disabled";
>> +        };
>> +
>> +        uart1: serial@10031000 {
>> +            compatible = "ingenic,x1000-uart";
>> +            reg = <0x10031000 0x100>;
>> +
>> +            interrupt-parent = <&intc>;
>> +            interrupts = <50>;
>> +
>> +            clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
>> +            clock-names = "baud", "module";
>> +
>> +            status = "disabled";
>> +        };
>> +
>> +        uart2: serial@10032000 {
>> +            compatible = "ingenic,x1000-uart";
>> +            reg = <0x10032000 0x100>;
>> +
>> +            interrupt-parent = <&intc>;
>> +            interrupts = <49>;
>> +
>> +            clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
>> +            clock-names = "baud", "module";
>> +
>> +            status = "disabled";
>> +        };
>> +
>> +        pinctrl: pin-controller@10010000 {
>> +            compatible = "ingenic,x1000-pinctrl";
>> +            reg = <0x10010000 0x800>;
>> +
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +
>> +            gpa: gpio@0 {
>> +                compatible = "ingenic,x1000-gpio";
>> +                reg = <0>;
>> +
>> +                gpio-controller;
>> +                gpio-ranges = <&pinctrl 0 0 32>;
>> +                #gpio-cells = <2>;
>> +
>> +                interrupt-controller;
>> +                #interrupt-cells = <2>;
>> +
>> +                interrupt-parent = <&intc>;
>> +                interrupts = <17>;
>> +            };
>> +
>> +            gpb: gpio@1 {
>> +                compatible = "ingenic,x1000-gpio";
>> +                reg = <1>;
>> +
>> +                gpio-controller;
>> +                gpio-ranges = <&pinctrl 0 32 32>;
>> +                #gpio-cells = <2>;
>> +
>> +                interrupt-controller;
>> +                #interrupt-cells = <2>;
>> +
>> +                interrupt-parent = <&intc>;
>> +                interrupts = <16>;
>> +            };
>> +
>> +            gpc: gpio@2 {
>> +                compatible = "ingenic,x1000-gpio";
>> +                reg = <2>;
>> +
>> +                gpio-controller;
>> +                gpio-ranges = <&pinctrl 0 64 32>;
>> +                #gpio-cells = <2>;
>> +
>> +                interrupt-controller;
>> +                #interrupt-cells = <2>;
>> +
>> +                interrupt-parent = <&intc>;
>> +                interrupts = <15>;
>> +            };
>> +
>> +            gpd: gpio@3 {
>> +                compatible = "ingenic,x1000-gpio";
>> +                reg = <3>;
>> +
>> +                gpio-controller;
>> +                gpio-ranges = <&pinctrl 0 96 32>;
>> +                #gpio-cells = <2>;
>> +
>> +                interrupt-controller;
>> +                #interrupt-cells = <2>;
>> +
>> +                interrupt-parent = <&intc>;
>> +                interrupts = <14>;
>> +            };
>> +        };
>> +    };
>> +};
>> diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
>> index 4dd0c44..6b96844 100644
>> --- a/arch/mips/jz4740/Kconfig
>> +++ b/arch/mips/jz4740/Kconfig
>> @@ -33,3 +33,9 @@ config MACH_JZ4780
>>      select MIPS_CPU_SCACHE
>>      select SYS_HAS_CPU_MIPS32_R2
>>      select SYS_SUPPORTS_HIGHMEM
>> +
>> +config MACH_X1000
>> +    bool
>> +    select MIPS_CPU_SCACHE
>> +    select SYS_HAS_CPU_MIPS32_R2
>> +    select SYS_SUPPORTS_HIGHMEM
>> diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
>> index cb768e5..3af6538 100644
>> --- a/arch/mips/jz4740/time.c
>> +++ b/arch/mips/jz4740/time.c
>> @@ -101,7 +101,9 @@ static struct clock_event_device 
>> jz4740_clockevent = {
>>  #ifdef CONFIG_MACH_JZ4740
>>      .irq = JZ4740_IRQ_TCU0,
>>  #endif
>> -#if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780)
>> +#if defined(CONFIG_MACH_JZ4770) || \
>> +    defined(CONFIG_MACH_JZ4780) || \
>> +    defined(CONFIG_MACH_X1000)
>
> That code was removed in the TCU patchset that was merged in time for 
> 5.4-rc1.
> Please rebase your patchset on top mips-next.
>

Thank you for your reminder, I will do it in v2.

Thanks and best regards!

> Cheers,
> -Paul
>
>




  reply	other threads:[~2019-11-22 15:11 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-22 13:11 Add initial support for Ingenic X1000 SoC and Y&A CU Neo board Zhou Yanjie
2019-11-22 13:11 ` [PATCH 1/4] MIPS: Ingenic: initial X1000 support Zhou Yanjie
2019-11-22 14:36   ` Paul Cercueil
2019-11-22 15:10     ` Zhou Yanjie [this message]
2019-11-22 13:11 ` [PATCH 2/4] dt-bindings: Document yna vendor-prefix Zhou Yanjie
2019-11-22 13:11 ` [PATCH 3/4] dt-bindings: MIPS: Add Ingenic XBurst based boards Zhou Yanjie
2019-11-22 13:11 ` [PATCH 4/4] MIPS: Ingenic: Initial YSH & ATIL CU Neo board support Zhou Yanjie

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