From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Jiwei Sun <jiwei.sun@windriver.com>,
ralf@linux-mips.org, paul.burton@imgtec.com,
james.hogan@imgtec.com
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
jiwei.sun.bj@qq.com
Subject: Re: [PATCH] MIPS: reset all task's asid to 0 after asid_cache(cpu) overflows
Date: Sun, 5 Mar 2017 12:38:09 +0300 [thread overview]
Message-ID: <6054d364-5095-d13b-ebf8-a7b6bf8b2024@cogentembedded.com> (raw)
In-Reply-To: <1488684260-18867-1-git-send-email-jiwei.sun@windriver.com>
Hello!
On 3/5/2017 6:24 AM, Jiwei Sun wrote:
> If asid_cache(cpu) overflows, there may be two tasks with the same
> asid. It is a risk that the two different tasks may have the same
> address space.
>
> A process will update its asid to newer version only when switch_mm()
> is called and matches the following condition:
> if ((cpu_context(cpu, next) ^ asid_cache(cpu))
> & asid_version_mask(cpu))
> get_new_mmu_context(next, cpu);
> If asid_cache(cpu) overflows, cpu_context(cpu,next) and asid_cache(cpu)
> will be reset to asid_first_version(cpu), and start a new cycle. It
> can result in two tasks that have the same ASID in the process list.
>
> For example, in CONFIG_CPU_MIPS32_R2, task named A's asid on CPU1 is
> 0x100, and has been sleeping and been not scheduled. After a long period
> of time, another running task named B's asid on CPU1 is 0xffffffff, and
> asid cached in the CPU1 is 0xffffffff too, next task named C is forked,
> when schedule from B to C on CPU1, asid_cache(cpu) will overflow, so C's
> asid on CPU1 will be 0x100 according to get_new_mmu_context(). A's asid
> is the same as C, if now A is rescheduled on CPU1, A's asid is not able
> to renew according to 'if' clause, and the local TLB entry can't be
> flushed too, A's address space will be the same as C.
>
> If asid_cache(cpu) overflows, all of user space task's asid on this CPU
> are able to set a invalid value (such as 0), it will avoid the risk.
>
> Signed-off-by: Jiwei Sun <jiwei.sun@windriver.com>
> ---
> arch/mips/include/asm/mmu_context.h | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
> index ddd57ad..1f60efc 100644
> --- a/arch/mips/include/asm/mmu_context.h
> +++ b/arch/mips/include/asm/mmu_context.h
> @@ -108,8 +108,15 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
> #else
> local_flush_tlb_all(); /* start new asid cycle */
> #endif
> - if (!asid) /* fix version if needed */
> + if (!asid) { /* fix version if needed */
> + struct task_struct *p;
> +
> + for_each_process(p) {
> + if ((p->mm))
Why double parens?
> + cpu_context(cpu, p->mm) = 0;
> + }
> asid = asid_first_version(cpu);
> + }
> }
>
> cpu_context(cpu, mm) = asid_cache(cpu) = asid;
MBR, Sergei
next prev parent reply other threads:[~2017-03-05 9:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-05 3:24 [PATCH] MIPS: reset all task's asid to 0 after asid_cache(cpu) overflows Jiwei Sun
2017-03-05 3:24 ` Jiwei Sun
2017-03-05 9:38 ` Sergei Shtylyov [this message]
2017-03-06 7:21 ` jsun4
2017-03-06 7:21 ` jsun4
2017-03-06 8:34 ` Sergei Shtylyov
2017-03-07 12:06 ` Jiwei Sun
2017-03-07 12:06 ` Jiwei Sun
2017-03-06 2:44 yhb
2017-03-06 2:44 ` yhb
2017-03-06 8:00 ` jsun4
2017-03-06 8:00 ` jsun4
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