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Thu, 25 Jun 2020 16:46:15 +0000 Received: from pps.filterd (aserp3020.oracle.com [127.0.0.1]) by aserp3020.oracle.com (8.16.0.42/8.16.0.42) with SMTP id 05PGcGPW056764; Thu, 25 Jun 2020 16:46:15 GMT Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by aserp3020.oracle.com with ESMTP id 31uur9sres-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 25 Jun 2020 16:46:14 +0000 Received: from abhmp0014.oracle.com (abhmp0014.oracle.com [141.146.116.20]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id 05PGk7fA012777; Thu, 25 Jun 2020 16:46:08 GMT Received: from [192.168.2.112] (/50.38.35.18) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 25 Jun 2020 16:46:07 +0000 Subject: Re: [PATCH 2/3] mm/huge_memory.c: update tlb entry if pmd is changed To: "Aneesh Kumar K.V" , Bibo Mao , Andrew Morton , Thomas Bogendoerfer , Paul Burton , Anshuman Khandual , Mike Rapoport , Daniel Silsby Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org References: <1592990792-1923-1-git-send-email-maobibo@loongson.cn> <1592990792-1923-2-git-send-email-maobibo@loongson.cn> <07f78e99-6e59-0bce-8ac0-50d7c7600461@oracle.com> <87lfkbl5gz.fsf@linux.ibm.com> From: Mike Kravetz Message-ID: <6071df89-1438-1a25-136d-228b8863364e@oracle.com> Date: Thu, 25 Jun 2020 09:46:06 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <87lfkbl5gz.fsf@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9663 signatures=668680 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=18 spamscore=0 adultscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006250104 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9663 signatures=668680 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=18 bulkscore=0 cotscore=-2147483648 malwarescore=0 mlxscore=0 clxscore=1011 lowpriorityscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006250104 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On 6/25/20 5:01 AM, Aneesh Kumar K.V wrote: > Mike Kravetz writes: > >> On 6/24/20 2:26 AM, Bibo Mao wrote: >>> When set_pmd_at is called in function do_huge_pmd_anonymous_page, >>> new tlb entry can be added by software on MIPS platform. >>> >>> Here add update_mmu_cache_pmd when pmd entry is set, and >>> update_mmu_cache_pmd is defined as empty excepts arc/mips platform. >>> This patch has no negative effect on other platforms except arc/mips >>> system. >> >> I am confused by this comment. It appears that update_mmu_cache_pmd >> is defined as non-empty on arc, mips, powerpc and sparc architectures. >> Am I missing something? >> >> If those architectures do provide update_mmu_cache_pmd, then the previous >> patch and this one now call update_mmu_cache_pmd with the actual faulting >> address instead of the huge page aligned address. This was intentional >> for mips. However, are there any potential issues on the other architectures? >> I am no expert in any of those architectures. arc looks like it could be >> problematic as update_mmu_cache_pmd calls update_mmu_cache and then >> operates on (address & PAGE_MASK). That could now be different. >> > > Also we added update_mmu_cache_pmd to update a THP entry. That could be > different from a hugetlb entry on some architectures. If we need to do > hugetlb equivalent for update_mmu_cache, we should add a different > function. I do not know the mips architecture well enough or if the motivation for this patch was based on THP or hugetlb pages. However, it will change the address passed to update_mmu_cache_pmd from huge page aligned to the actual faulting address. Will such a change in the passed address impact the powerpc update_mmu_cache_pmd routine? -- Mike Kravetz