From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60622C433EF for ; Tue, 9 Nov 2021 20:36:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4200561184 for ; Tue, 9 Nov 2021 20:36:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244476AbhKIUjN convert rfc822-to-8bit (ORCPT ); Tue, 9 Nov 2021 15:39:13 -0500 Received: from aposti.net ([89.234.176.197]:52358 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244036AbhKIUjN (ORCPT ); Tue, 9 Nov 2021 15:39:13 -0500 Date: Tue, 09 Nov 2021 20:36:06 +0000 From: Paul Cercueil Subject: Re: [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers To: "H. Nikolaus Schaller" Cc: Paul Boddie , Rob Herring , Mark Rutland , Thomas Bogendoerfer , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil , Liam Girdwood , Mark Brown , OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS , linux-mips , linux-kernel , Discussions about the Letux Kernel , Jon as Karlman , dri-devel Message-Id: <6WNB2R.GJ2KT1BB7QOY1@crapouillou.net> In-Reply-To: References: <3514743.EH6qe8WxYI@jason> <95D1DE70-DDF4-419B-8F0C-E9A6E0995D1F@goldelico.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Hi Nikolaus, Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller a écrit : > Hi Paul, > >> Am 07.11.2021 um 20:05 schrieb Paul Cercueil : >> >>> 6. Therefore I think it *may* work overclocked with 48MHz >>> but is not guaranteed or reliable above 27 MHz. >>> So everything is ok here. >> >> One thing though - the "assigned-clocks" and >> "assigned-clock-rates", while it works here, should be moved to the >> CGU node, to respect the YAML schemas. > > Trying to do this seems to break boot. > > I can boot up to > > [ 8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare > HDMI I2C bus driver > > and > > [ 11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for > 13050000.lcdc0 on minor 0 > > but then the boot process becomes slow and hangs. Last sign of > activity is > > [ 19.347659] hub 1-0:1.0: USB hub found > [ 19.353478] hub 1-0:1.0: 1 port detected > [ 32.321760] wlan0_power: disabling > > What I did was to just move > > assigned-clocks = <&cgu JZ4780_CLK_HDMI>; > assigned-clock-rates = <27000000>; > > from > > hdmi: hdmi@10180000 { > > to > > cgu: jz4780-cgu@10000000 { > > Does this mean the clock is assigned too early or too late? > > Do you have any suggestions since I don't know the details of CGU. These properties are already set for the CGU node in ci20.dts: &cgu { /* * Use the 32.768 kHz oscillator as the parent of the RTC for a higher * precision. */ assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>; assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>; assigned-clock-rates = <48000000>; }; So you want to update these properties to add the HDMI clock setting, like this: assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, <&cgu JZ4780_CLK_HDMI>; assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>; assigned-clock-rates = <48000000>, <0>, <27000000>; Cheers, -Paul