From: Alexander Lobakin <aleksander.lobakin@intel.com>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH 04/12] MIPS: Octeon: Opt-out 4k_cache feature
Date: Tue, 7 Mar 2023 17:51:32 +0100 [thread overview]
Message-ID: <748e9714-b245-9d61-7c28-fd38c726b9a6@intel.com> (raw)
In-Reply-To: <A09E74C0-BA5A-4BAA-B6DD-74109090A153@flygoat.com>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Mon, 6 Mar 2023 19:55:23 +0000
>
>
>> 2023年3月6日 14:28,Alexander Lobakin <aleksander.lobakin@intel.com> 写道:
>>
>> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Date: Sat, 4 Mar 2023 22:15:16 +0000
>>
>>> Octeon has a different cache interface with traditional R4K one,
>>> just opt-out this flag for octeon to avoid run R4K cache initialization
>>> code accidentally.
>>>
>>> Also remove ISA level assumption for 4k cache.
>>>
>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>> ---
>>> arch/mips/include/asm/cpu-features.h | 2 +-
>>> arch/mips/kernel/cpu-probe.c | 2 ++
>>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
>>> index c0983130a44c..c613426b0bfc 100644
>>> --- a/arch/mips/include/asm/cpu-features.h
>>> +++ b/arch/mips/include/asm/cpu-features.h
>>> @@ -118,7 +118,7 @@
>>> #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
>>> #endif
>>> #ifndef cpu_has_4k_cache
>>> -#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
>>> +#define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE)
>>
>> This breaks compile-time optimization for this feature => hurts
>> performance on non-Octeon machines. Could this be done some other way?
>> E.g. could this be defined depending on
>> CONFIG_SYS_HAS_CPU_OCTEON_WHATEVER? Via its own cpu-features.h or here,
>> that's the second question. So that the platforms which 100% can't have
>> this family of CPUs wouldn't get affected.
>
> Thanks for the comment.
>
> This feature is only checked once during boot and never checked at runtime so I think impact
> should be negligible.
Ah, didn't notice it's not used anywhere on hotpath. Just forgot that
MIPS installs cache sync callbacks once at boot and then use them.
>
> Just don’t want to have another ifdef here :-)
I'm not sure one ifdef would hurt, we probably need a third opinion here
:D Maybe Thomas'. But I'm fine with the current implementation.
>
>
> Thanks
> - Jiaxun
Thanks,
Olek
next prev parent reply other threads:[~2023-03-07 16:56 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-04 22:15 [PATCH 00/12] MIPS Virt board support Jiaxun Yang
2023-03-04 22:15 ` [PATCH 01/12] MIPS: Move declaration of bcache ops to cache.c Jiaxun Yang
2023-03-04 22:15 ` [PATCH 02/12] MIPS: smp-cps: Disable coherence setup for unsupported ISA Jiaxun Yang
2023-03-04 22:15 ` [PATCH 03/12] MIPS: mips-cm: Check availability of config registers Jiaxun Yang
2023-03-04 22:15 ` [PATCH 04/12] MIPS: Octeon: Opt-out 4k_cache feature Jiaxun Yang
2023-03-06 14:28 ` Alexander Lobakin
2023-03-06 19:55 ` Jiaxun Yang
2023-03-07 16:51 ` Alexander Lobakin [this message]
2023-03-04 22:15 ` [PATCH 05/12] MIPS: cpu-features: Enable octeon_cache by cpu_type Jiaxun Yang
2023-03-04 22:15 ` [PATCH 06/12] MIPS: c-octeon: Provide alternative SMP cache flush function Jiaxun Yang
2023-03-05 8:41 ` Sergei Shtylyov
2023-03-04 22:15 ` [PATCH 07/12] MIPS: Octeon: Allow CVMSEG to be disabled Jiaxun Yang
2023-03-04 22:15 ` [PATCH 08/12] MIPS: Loongson: Move arch cflags to MIPS top level Makefile Jiaxun Yang
2023-03-04 22:15 ` [PATCH 09/12] MIPS: Loongson: Don't select platform features with CPU Jiaxun Yang
2023-03-04 22:15 ` [PATCH 10/12] MIPS: Octeon: Disable CVMSEG by default on other platforms Jiaxun Yang
2023-03-04 22:15 ` [PATCH 11/12] MIPS: Add board config for virt board Jiaxun Yang
2023-03-04 22:15 ` [PATCH 12/12] MIPS: generic: Enable all CPUs supported by virt board in Kconfig Jiaxun Yang
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