* [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer
@ 2020-09-23 11:02 Jiaxun Yang
2020-10-02 13:27 ` Thomas Bogendoerfer
2020-10-04 20:49 ` Paul Cercueil
0 siblings, 2 replies; 5+ messages in thread
From: Jiaxun Yang @ 2020-09-23 11:02 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Huacai Chen, Serge Semin,
Alexey Malahov, WANG Xuerui, Paul Burton,
周琰杰 (Zhou Yanjie),
afzal mohammed, Paul Cercueil, Liangliang Huang, linux-kernel
Loongson64C and Loongson64G have extimer feature, which is a
timer sharing Cause.TI with cevt-r4k (named intimer).
To ensure the cevt-r4k's usability, we need to add a callback for
clock device to switch intimer.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/cpu-features.h | 4 ++++
arch/mips/include/asm/cpu.h | 1 +
arch/mips/kernel/cevt-r4k.c | 25 +++++++++++++++++++++++++
arch/mips/kernel/cpu-probe.c | 6 +++++-
4 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 78cf7e300f12..aec458eee2a5 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -576,6 +576,10 @@
# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX)
#endif
+#ifndef cpu_has_extimer
+# define cpu_has_extimer __opt(MIPS_CPU_EXTIMER)
+#endif
+
#ifdef CONFIG_SMP
/*
* Some systems share FTLB RAMs between threads within a core (siblings in
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 388a82f28a87..854e1b44254b 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -429,6 +429,7 @@ enum cpu_type_enum {
#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
+#define MIPS_CPU_EXTIMER BIT_ULL(63) /* CPU has External Timer (Loongson) */
/*
* CPU ASE encodings
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 995ad9e69ded..fae49e9215b4 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,8 @@
#include <asm/time.h>
#include <asm/cevt-r4k.h>
+#include <asm/cpu-features.h>
+#include <asm/mipsregs.h>
static int mips_next_event(unsigned long delta,
struct clock_event_device *evt)
@@ -294,6 +296,24 @@ core_initcall(r4k_register_cpufreq_notifier);
#endif /* !CONFIG_CPU_FREQ */
+#ifdef CONFIG_CPU_LOONGSON64
+static int c0_compare_int_enable(struct clock_event_device *cd)
+{
+ if (cpu_has_extimer)
+ set_c0_config6(LOONGSON_CONF6_INTIMER);
+
+ return 0;
+}
+
+static int c0_compare_int_disable(struct clock_event_device *cd)
+{
+ if (cpu_has_extimer)
+ clear_c0_config6(LOONGSON_CONF6_INTIMER);
+
+ return 0;
+}
+#endif
+
int r4k_clockevent_init(void)
{
unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
@@ -329,6 +349,11 @@ int r4k_clockevent_init(void)
cd->set_next_event = mips_next_event;
cd->event_handler = mips_event_handler;
+#ifdef CONFIG_CPU_LOONGSON64
+ cd->set_state_oneshot = c0_compare_int_enable;
+ cd->set_state_shutdown = c0_compare_int_disable;
+#endif
+
clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
if (cp0_timer_irq_installed)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6be23f205e74..4f1e9ef2644e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2030,6 +2030,9 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c)
if (cfg2 & LOONGSON_CFG2_LEXT2)
c->ases |= MIPS_ASE_LOONGSON_EXT2;
+ if (cfg2 & LOONGSON_CFG2_LLFTP)
+ c->options |= MIPS_CPU_EXTIMER;
+
if (cfg2 & LOONGSON_CFG2_LSPW) {
c->options |= MIPS_CPU_LDPTE;
c->guest.options |= MIPS_CPU_LDPTE;
@@ -2088,7 +2091,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
* Also some early Loongson-3A2000 had wrong TLB type in Config
* register, we correct it here.
*/
- c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
+ c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE |
+ MIPS_CPU_EXTIMER;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
--
2.28.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer
2020-09-23 11:02 [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer Jiaxun Yang
@ 2020-10-02 13:27 ` Thomas Bogendoerfer
2020-10-03 6:25 ` Jiaxun Yang
2020-10-04 20:49 ` Paul Cercueil
1 sibling, 1 reply; 5+ messages in thread
From: Thomas Bogendoerfer @ 2020-10-02 13:27 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, Huacai Chen, Serge Semin, Alexey Malahov,
WANG Xuerui, Paul Burton, 周琰杰 (Zhou Yanjie),
afzal mohammed, Paul Cercueil, Liangliang Huang, linux-kernel
On Wed, Sep 23, 2020 at 07:02:54PM +0800, Jiaxun Yang wrote:
>
> +#ifdef CONFIG_CPU_LOONGSON64
> +static int c0_compare_int_enable(struct clock_event_device *cd)
> +{
> + if (cpu_has_extimer)
> + set_c0_config6(LOONGSON_CONF6_INTIMER);
why are you not simply do this in loognson64 board setup code and avoid
the whole cluttering of #ifdef CONFIG_CPU_LOONGSON64 over common code ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer
2020-10-02 13:27 ` Thomas Bogendoerfer
@ 2020-10-03 6:25 ` Jiaxun Yang
2020-10-04 20:12 ` Thomas Bogendoerfer
0 siblings, 1 reply; 5+ messages in thread
From: Jiaxun Yang @ 2020-10-03 6:25 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Huacai Chen, Serge Semin, Alexey Malahov,
WANG Xuerui, Paul Burton, 周琰杰 (Zhou Yanjie),
afzal mohammed, Paul Cercueil, Liangliang Huang, linux-kernel
于 2020年10月2日 GMT+08:00 下午9:27:21, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
>On Wed, Sep 23, 2020 at 07:02:54PM +0800, Jiaxun Yang wrote:
>>
>> +#ifdef CONFIG_CPU_LOONGSON64
>> +static int c0_compare_int_enable(struct clock_event_device *cd)
>> +{
>> + if (cpu_has_extimer)
>> + set_c0_config6(LOONGSON_CONF6_INTIMER);
>
>why are you not simply do this in loognson64 board setup code and avoid
>the whole cluttering of #ifdef CONFIG_CPU_LOONGSON64 over common code ?
Because I'm going to add extimer support later that require dynamic switch of cevt-r4k.
This callback is required.
Thanks.
- Jiaxun
>
>Thomas.
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer
2020-10-03 6:25 ` Jiaxun Yang
@ 2020-10-04 20:12 ` Thomas Bogendoerfer
0 siblings, 0 replies; 5+ messages in thread
From: Thomas Bogendoerfer @ 2020-10-04 20:12 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, Huacai Chen, Serge Semin, Alexey Malahov,
WANG Xuerui, Paul Burton, 周琰杰 (Zhou Yanjie),
afzal mohammed, Paul Cercueil, Liangliang Huang, linux-kernel
On Sat, Oct 03, 2020 at 02:25:42PM +0800, Jiaxun Yang wrote:
>
>
> 于 2020年10月2日 GMT+08:00 下午9:27:21, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
> >On Wed, Sep 23, 2020 at 07:02:54PM +0800, Jiaxun Yang wrote:
> >>
> >> +#ifdef CONFIG_CPU_LOONGSON64
> >> +static int c0_compare_int_enable(struct clock_event_device *cd)
> >> +{
> >> + if (cpu_has_extimer)
> >> + set_c0_config6(LOONGSON_CONF6_INTIMER);
> >
> >why are you not simply do this in loognson64 board setup code and avoid
> >the whole cluttering of #ifdef CONFIG_CPU_LOONGSON64 over common code ?
>
> Because I'm going to add extimer support later that require dynamic
> switch of cevt-r4k.
another case of misdesigned hardware or why does this need to be
dynamic ?
> This callback is required.
please find a solution without #ifdef CONFIG_CPU_LOONGSON64. I dislike
the pollution of common code with all kinds of #ifdefs and in this case
there are better options.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer
2020-09-23 11:02 [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer Jiaxun Yang
2020-10-02 13:27 ` Thomas Bogendoerfer
@ 2020-10-04 20:49 ` Paul Cercueil
1 sibling, 0 replies; 5+ messages in thread
From: Paul Cercueil @ 2020-10-04 20:49 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, Thomas Bogendoerfer, Huacai Chen, Serge Semin,
Alexey Malahov, WANG Xuerui, Paul Burton,
周琰杰,
afzal mohammed, Liangliang Huang, linux-kernel
Hi,
Le mer. 23 sept. 2020 à 19:02, Jiaxun Yang <jiaxun.yang@flygoat.com> a
écrit :
> Loongson64C and Loongson64G have extimer feature, which is a
> timer sharing Cause.TI with cevt-r4k (named intimer).
>
> To ensure the cevt-r4k's usability, we need to add a callback for
> clock device to switch intimer.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> arch/mips/include/asm/cpu-features.h | 4 ++++
> arch/mips/include/asm/cpu.h | 1 +
> arch/mips/kernel/cevt-r4k.c | 25 +++++++++++++++++++++++++
> arch/mips/kernel/cpu-probe.c | 6 +++++-
> 4 files changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/cpu-features.h
> b/arch/mips/include/asm/cpu-features.h
> index 78cf7e300f12..aec458eee2a5 100644
> --- a/arch/mips/include/asm/cpu-features.h
> +++ b/arch/mips/include/asm/cpu-features.h
> @@ -576,6 +576,10 @@
> # define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX)
> #endif
>
> +#ifndef cpu_has_extimer
> +# define cpu_has_extimer __opt(MIPS_CPU_EXTIMER)
> +#endif
> +
> #ifdef CONFIG_SMP
> /*
> * Some systems share FTLB RAMs between threads within a core
> (siblings in
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index 388a82f28a87..854e1b44254b 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -429,6 +429,7 @@ enum cpu_type_enum {
> #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support
> MAC2008 Fused multiply-add instruction */
> #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity
> exception */
> #define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
> +#define MIPS_CPU_EXTIMER BIT_ULL(63) /* CPU has External Timer
> (Loongson) */
>
> /*
> * CPU ASE encodings
> diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
> index 995ad9e69ded..fae49e9215b4 100644
> --- a/arch/mips/kernel/cevt-r4k.c
> +++ b/arch/mips/kernel/cevt-r4k.c
> @@ -15,6 +15,8 @@
>
> #include <asm/time.h>
> #include <asm/cevt-r4k.h>
> +#include <asm/cpu-features.h>
> +#include <asm/mipsregs.h>
>
> static int mips_next_event(unsigned long delta,
> struct clock_event_device *evt)
> @@ -294,6 +296,24 @@ core_initcall(r4k_register_cpufreq_notifier);
>
> #endif /* !CONFIG_CPU_FREQ */
>
> +#ifdef CONFIG_CPU_LOONGSON64
> +static int c0_compare_int_enable(struct clock_event_device *cd)
> +{
> + if (cpu_has_extimer)
> + set_c0_config6(LOONGSON_CONF6_INTIMER);
> +
> + return 0;
> +}
> +
> +static int c0_compare_int_disable(struct clock_event_device *cd)
> +{
> + if (cpu_has_extimer)
> + clear_c0_config6(LOONGSON_CONF6_INTIMER);
> +
> + return 0;
> +}
> +#endif
static int __maybe_unused c0_compare_int_enable(...)
{
...
}
without the #ifdef.
Or better, move these two to loongson64 board code, with "extern int
c0_compare_int_enable" in a header somewhere.
> +
> int r4k_clockevent_init(void)
> {
> unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
> @@ -329,6 +349,11 @@ int r4k_clockevent_init(void)
> cd->set_next_event = mips_next_event;
> cd->event_handler = mips_event_handler;
>
> +#ifdef CONFIG_CPU_LOONGSON64
> + cd->set_state_oneshot = c0_compare_int_enable;
> + cd->set_state_shutdown = c0_compare_int_disable;
> +#endif
> +
if (IS_ENABLED(CONFIG_CPU_LOONGSON64)) {
cd->set_state_oneshot = ...;
}
Although I think this is still incorrect: here you check whether the
kernel supports this CPU, instead of checking what CPU you're running
on.
Cheers,
-Paul
> clockevents_config_and_register(cd, mips_hpt_frequency, min_delta,
> 0x7fffffff);
>
> if (cp0_timer_irq_installed)
> diff --git a/arch/mips/kernel/cpu-probe.c
> b/arch/mips/kernel/cpu-probe.c
> index 6be23f205e74..4f1e9ef2644e 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -2030,6 +2030,9 @@ static inline void decode_cpucfg(struct
> cpuinfo_mips *c)
> if (cfg2 & LOONGSON_CFG2_LEXT2)
> c->ases |= MIPS_ASE_LOONGSON_EXT2;
>
> + if (cfg2 & LOONGSON_CFG2_LLFTP)
> + c->options |= MIPS_CPU_EXTIMER;
> +
> if (cfg2 & LOONGSON_CFG2_LSPW) {
> c->options |= MIPS_CPU_LDPTE;
> c->guest.options |= MIPS_CPU_LDPTE;
> @@ -2088,7 +2091,8 @@ static inline void cpu_probe_loongson(struct
> cpuinfo_mips *c, unsigned int cpu)
> * Also some early Loongson-3A2000 had wrong TLB type in Config
> * register, we correct it here.
> */
> - c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
> + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE |
> + MIPS_CPU_EXTIMER;
> c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
> MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
> --
> 2.28.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-10-04 20:50 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-23 11:02 [PATCH] MIPS: cevt-r4k: Enable intimer for Loongson64 CPUs with extimer Jiaxun Yang
2020-10-02 13:27 ` Thomas Bogendoerfer
2020-10-03 6:25 ` Jiaxun Yang
2020-10-04 20:12 ` Thomas Bogendoerfer
2020-10-04 20:49 ` Paul Cercueil
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).