From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0118EC282C7 for ; Sat, 26 Jan 2019 12:09:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C3368218A6 for ; Sat, 26 Jan 2019 12:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726218AbfAZMJX (ORCPT ); Sat, 26 Jan 2019 07:09:23 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:57862 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726165AbfAZMJX (ORCPT ); Sat, 26 Jan 2019 07:09:23 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D2A5EA78; Sat, 26 Jan 2019 04:09:22 -0800 (PST) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B9F3E3F5C1; Sat, 26 Jan 2019 04:09:20 -0800 (PST) Date: Sat, 26 Jan 2019 12:09:18 +0000 Message-ID: <868sz78vtd.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Jiaxun Yang Cc: linux-mips@vger.kernel.org, tglx@linutronix.de, jason@lakedaemon.net, robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 1/2] irqchip: Add driver for Loongson-1 interrupt controller In-Reply-To: References: <20190122154557.22689-1-jiaxun.yang@flygoat.com> <20190124032730.18237-1-jiaxun.yang@flygoat.com> <20190124032730.18237-2-jiaxun.yang@flygoat.com> <86pnsm8jon.wl-marc.zyngier@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Fri, 25 Jan 2019 10:56:33 +0000, Jiaxun Yang wrote: > > Hi Marc > > Thanks for your suggestions, I'm working on v4 and I would like to > ask if it is better to have a driver for only one irqchip and create > dt nodes for each chip, or just register all the chips in a single > driver with only one dt node. It would make more sense to have a node per chip, meaning that you end-up with one instance per chip as well. It won't make the driver much more complicated. [...] > >> + domain = irq_domain_add_legacy(node, num_chips * 32, LS1X_IRQ_BASE, 0, > >> + &irq_domain_simple_ops, NULL); > > Why a legacy domain? This is usually reserved to old drivers that are > > converted to a new infrastructure, while needing some form of platform > > hacks. I don't see this being the case here. > > > > It is also worrying that although you have up to 5 irqchips, they all > > share a single domain. What does this mean? each irqchip is expected > > to have its own domain. > > Yes, I do like this for backward compatible reason. I'm turning > a legacy platform device mach(arch/mips/loongson32) in to > dt based generic mach and I would like to do it step by step rather > than one time. > > So I use legacy domain in order to keep IRQ same with the > old driver exist on arch/mips/loongson32/common/irq.c OK, it would have been good to make a note of that in the cover letter, which is a bit empty at the moment. Thanks, M. -- Jazz is not dead, it just smell funny.