From: Marc Zyngier <marc.zyngier@arm.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: tglx@linutronix.de, jason@lakedaemon.net, ralf@linux-mips.org,
paul.burton@mips.com, jhogan@kernel.org, robh+dt@kernel.org,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, mark.rutland@arm.com,
john@phrozen.org, hauke@hauke-m.de
Subject: Re: [PATCH 5/5] MIPS: dts: lantiq: danube: easy50712: route the PCI_INTA IRQ through EBU
Date: Sun, 28 Jul 2019 11:03:31 +0100 [thread overview]
Message-ID: <86wog2mq6k.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <20190727175315.28834-6-martin.blumenstingl@googlemail.com>
On Sat, 27 Jul 2019 18:53:15 +0100,
Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
> EBU provides an interrupt line for the PCI_INTA interrupt. Route
> easy50712's PCI interrupt to EBU so the interrupt line is configured
> correctly (using IRQ_TYPE_LEVEL_LOW, this was previously hardcoded in
> the PCI driver) and ACKed properly.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> arch/mips/boot/dts/lantiq/easy50712.dts | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/dts/lantiq/easy50712.dts b/arch/mips/boot/dts/lantiq/easy50712.dts
> index 1ce20b7d05cb..33c26b93cfc9 100644
> --- a/arch/mips/boot/dts/lantiq/easy50712.dts
> +++ b/arch/mips/boot/dts/lantiq/easy50712.dts
> @@ -1,6 +1,8 @@
> // SPDX-License-Identifier: GPL-2.0
> /dts-v1/;
>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> /include/ "danube.dtsi"
>
> / {
> @@ -105,7 +107,7 @@
> lantiq,bus-clock = <33333333>;
> interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
> interrupt-map = <
> - 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
> + 0x7000 0 0 1 &ebu0 0 IRQ_TYPE_LEVEL_LOW // slot 14
> >;
> gpios-reset = <&gpio 21 0>;
> req-mask = <0x1>; /* GNT1 */
> --
> 2.22.0
>
Are you OK with breaking compatibility between kernel and DT? It
usually isn't very nice for users...
Thanks,
M.
--
Jazz is not dead, it just smells funny.
next prev parent reply other threads:[~2019-07-28 10:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-27 17:53 [PATCH 0/5] MIPS: lantiq: EBU interrupt controller and generalization Martin Blumenstingl
2019-07-27 17:53 ` [PATCH 1/5] dt-bindings: MIPS: lantiq: Add documentation for the External Bus Unit Martin Blumenstingl
2019-07-29 23:17 ` Rob Herring
2019-07-27 17:53 ` [PATCH 2/5] MIPS: lantiq: use a generic "EBU" driver for Falcon and XWAY SoCs Martin Blumenstingl
2019-07-27 18:35 ` John Crispin
2019-07-27 18:37 ` Martin Blumenstingl
2019-07-27 17:53 ` [PATCH 3/5] MIPS: lantiq: add an irq_domain and irq_chip for EBU Martin Blumenstingl
2019-07-28 10:01 ` Marc Zyngier
2019-08-01 17:42 ` Martin Blumenstingl
2019-08-03 9:12 ` Marc Zyngier
2019-08-03 17:33 ` Martin Blumenstingl
2019-08-05 15:03 ` Marc Zyngier
2019-07-27 17:53 ` [PATCH 4/5] MIPS: dts: lantiq: danube: mark the ebu0 node as interrupt-controller Martin Blumenstingl
2019-07-27 17:53 ` [PATCH 5/5] MIPS: dts: lantiq: danube: easy50712: route the PCI_INTA IRQ through EBU Martin Blumenstingl
2019-07-28 10:03 ` Marc Zyngier [this message]
2019-07-29 21:55 ` Hauke Mehrtens
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