From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 447E1C433F5 for ; Sun, 7 Nov 2021 13:46:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1AD88600CD for ; Sun, 7 Nov 2021 13:46:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235414AbhKGNsm (ORCPT ); Sun, 7 Nov 2021 08:48:42 -0500 Received: from mo4-p03-ob.smtp.rzone.de ([81.169.146.175]:14529 "EHLO mo4-p03-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230128AbhKGNsm (ORCPT ); Sun, 7 Nov 2021 08:48:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1636292738; s=strato-dkim-0002; d=goldelico.com; h=To:References:Message-Id:Cc:Date:In-Reply-To:From:Subject:Cc:Date: From:Subject:Sender; bh=IUc2QJfZvKVpNPLQO06V15aBwBXtE3TaY9v9c4KrZsM=; b=fqLzXb2UhysqRDNzD+S2Zk+/MroOToOZvONeUoHdL6Rz3bvRrcp8MugsYf2DJZseIy pZtVfccDMOcNmS/UHbz8Ad4+N4objU7P/umYVohzmQjVhXYqOfyKK6mmu50MGaTxsV5g s6BjUUecIKnZqmqPx1f+kVKRAO9CSM+l55uMxaNyUseep29yQs2rwpRODEt5pZ1eWyS6 fwHOO4r3ry2q0aYUc6oYnSVPhVtCAY9zI8+ZAG9z8LoO9fIp7D2MDRWji4qKlt5gwPWH ZCKBlG9KiONzEKmQR6FtJIgIw41OjTtsnw2zS0+8hyG7ltSEm5C9r6pjfmIhi/W52JnA iMkw== Authentication-Results: strato.com; dkim=none X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMgPgp8VKxflSZ1P34KBj7gpw91N5y2S3jcR+" X-RZG-CLASS-ID: mo00 Received: from imac.fritz.box by smtp.strato.de (RZmta 47.34.1 DYNA|AUTH) with ESMTPSA id 902c63xA7DjcFoL (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve X9_62_prime256v1 with 256 ECDH bits, eq. 3072 bits RSA)) (Client did not present a certificate); Sun, 7 Nov 2021 14:45:38 +0100 (CET) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 12.4 \(3445.104.21\)) Subject: Re: [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers From: "H. Nikolaus Schaller" In-Reply-To: Date: Sun, 7 Nov 2021 14:45:37 +0100 Cc: Paul Boddie , Rob Herring , Mark Rutland , Thomas Bogendoerfer , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil , Liam Girdwood , Mark Brown , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-mips , linux-kernel , Discussions about the Letux Kernel , Jon as Karlman , dri-devel Content-Transfer-Encoding: quoted-printable Message-Id: <95D1DE70-DDF4-419B-8F0C-E9A6E0995D1F@goldelico.com> References: <3514743.EH6qe8WxYI@jason> To: Paul Cercueil X-Mailer: Apple Mail (2.3445.104.21) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Hi Paul, > Am 05.10.2021 um 23:52 schrieb Paul Cercueil : >=20 > Hi Paul, >=20 > Le mar., oct. 5 2021 at 23:44:12 +0200, Paul Boddie = a =C3=A9crit : >> On Tuesday, 5 October 2021 22:50:12 CEST Paul Cercueil wrote: >>> Hi Nikolaus & Paul, >>> Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller >> a =C3=A9crit : >>> > >>> > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > b/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > index 9e34f433b9b5..c3c18a59c377 100644 >>> > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 { >>> > >>> > status =3D "disabled"; >>> > >>> > }; >>> > >>> > + hdmi: hdmi@10180000 { >>> > + compatible =3D "ingenic,jz4780-dw-hdmi"; >>> > + reg =3D <0x10180000 0x8000>; >>> > + reg-io-width =3D <4>; >>> > + >>> > + clocks =3D <&cgu JZ4780_CLK_AHB0>, <&cgu = JZ4780_CLK_HDMI>; >>> > + clock-names =3D "iahb", "isfr"; >>> > + >>> > + assigned-clocks =3D <&cgu JZ4780_CLK_HDMI>; >>> > + assigned-clock-rates =3D <27000000>; >>> Any reason why this is set to 27 MHz? Is it even required? Because = with >>> the current ci20.dts, it won't be clocked at anything but 48 MHz. >> EXCLK will be 48MHz, but the aim is to set the HDMI peripheral clock = to 27MHz, >> which is supposedly required. I vaguely recall a conversation about = whether we >> were doing this right, but I don't recall any conclusion. >=20 > But right now your HDMI clock is 48 MHz and HDMI works. Is it? How did you find out? And have you tried to remove assigned-clocks from jz4780.dtsi? 1. I read back: root@letux:~# cat /sys/kernel/debug/clk/hdmi/clk_rate 26909090 root@letux:~#=20 So for me it seems to be running at ~27 MHz. 2. If I remove the assigned-clocks or assigned-clock-rates from DT the boot process hangs shortly after initializing drm. 3. If I set assigned-clock-rates =3D <48000000>, HDMI also works. I get it read back from /sys/kernel/debug/clk/hdmi/clk_rate of 46736842. 4. Conclusions: * assigned-clocks are required * it does not matter if 27 or 48 MHz * I have no idea which value is more correct * so I'd stay on the safe side of 27 MHz 5. But despite that found, please look into the programming manual section 18.1.2.16. There is an "Import Note: The clock must be between 18M and 27M, it occurs fatal error if exceeding the range. " 6. Therefore I think it *may* work overclocked with 48MHz but is not guaranteed or reliable above 27 MHz. So everything is ok here. >=20 >>> > + >>> > + interrupt-parent =3D <&intc>; >>> > + interrupts =3D <3>; >>> > + >>> > + /* ddc-i2c-bus =3D <&i2c4>; */ >>> > + >>> > + status =3D "disabled"; >>> > + }; >>> > + >>> > + lcdc0: lcdc0@13050000 { >>> > + compatible =3D "ingenic,jz4780-lcd"; >>> > + reg =3D <0x13050000 0x1800>; >>> > + >>> > + clocks =3D <&cgu JZ4780_CLK_TVE>, <&cgu = JZ4780_CLK_LCD0PIXCLK>; >>> > + clock-names =3D "lcd", "lcd_pclk"; >>> > + >>> > + interrupt-parent =3D <&intc>; >>> > + interrupts =3D <31>; >>> > + >>> > + status =3D "disabled"; >>> I think you can keep lcdc0 enabled by default (not lcdc1 though), = since >>> it is highly likely that you'd want that. >> As far as I know, the clock gating for the LCD controllers acts like = a series >> circuit, meaning that they both need to be enabled. Some testing = seemed to >> confirm this. Indeed, I seem to remember only enabling one clock and = not >> getting any output until I figured this weird arrangement out. >=20 > I'm not talking about clocks though, but about LCDC0 and LCDC1. Ah, you mean status =3D "okay"; vs. status =3D "disabled"; Well, IMHO it is common practise to keep SoC subsystems disabled by default (to save power and boot time) unless a board specific DTS = explicitly requests the SoC feature to be active. See for example mmc0, mmc1 or = i2c0..i2c4. All these are disabled in jz4780.dtsi and partially enabled in ci20.dts. Why should lcdc0 be an exception in jz4780.dtsi? BR and thanks, Nikolaus