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Mon, 6 Mar 2023 14:55:35 -0500 (EST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3731.400.51.1.1\)) Subject: Re: [PATCH 04/12] MIPS: Octeon: Opt-out 4k_cache feature From: Jiaxun Yang In-Reply-To: Date: Mon, 6 Mar 2023 19:55:23 +0000 Cc: "linux-mips@vger.kernel.org" , Thomas Bogendoerfer , =?utf-8?Q?Philippe_Mathieu-Daud=C3=A9?= Content-Transfer-Encoding: quoted-printable Message-Id: References: <20230304221524.47160-1-jiaxun.yang@flygoat.com> <20230304221524.47160-5-jiaxun.yang@flygoat.com> To: Alexander Lobakin X-Mailer: Apple Mail (2.3731.400.51.1.1) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org > 2023=E5=B9=B43=E6=9C=886=E6=97=A5 14:28=EF=BC=8CAlexander Lobakin = =E5=86=99=E9=81=93=EF=BC=9A >=20 > From: Jiaxun Yang > Date: Sat, 4 Mar 2023 22:15:16 +0000 >=20 >> Octeon has a different cache interface with traditional R4K one, >> just opt-out this flag for octeon to avoid run R4K cache = initialization >> code accidentally. >>=20 >> Also remove ISA level assumption for 4k cache. >>=20 >> Signed-off-by: Jiaxun Yang >> --- >> arch/mips/include/asm/cpu-features.h | 2 +- >> arch/mips/kernel/cpu-probe.c | 2 ++ >> 2 files changed, 3 insertions(+), 1 deletion(-) >>=20 >> diff --git a/arch/mips/include/asm/cpu-features.h = b/arch/mips/include/asm/cpu-features.h >> index c0983130a44c..c613426b0bfc 100644 >> --- a/arch/mips/include/asm/cpu-features.h >> +++ b/arch/mips/include/asm/cpu-features.h >> @@ -118,7 +118,7 @@ >> #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) >> #endif >> #ifndef cpu_has_4k_cache >> -#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) >> +#define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE) >=20 > This breaks compile-time optimization for this feature =3D> hurts > performance on non-Octeon machines. Could this be done some other way? > E.g. could this be defined depending on > CONFIG_SYS_HAS_CPU_OCTEON_WHATEVER? Via its own cpu-features.h or = here, > that's the second question. So that the platforms which 100% can't = have > this family of CPUs wouldn't get affected. Thanks for the comment. This feature is only checked once during boot and never checked at = runtime so I think impact should be negligible. Just don=E2=80=99t want to have another ifdef here :-) Thanks - Jiaxun=