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* Ingenic pinctrl fixes.
@ 2019-01-25  9:59 Zhou Yanjie
  2019-01-25  9:59 ` [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
                   ` (4 more replies)
  0 siblings, 5 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-25  9:59 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199

Resend because previous mail is blocked by server.



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.
  2019-01-25  9:59 Ingenic pinctrl fixes Zhou Yanjie
@ 2019-01-25  9:59 ` Zhou Yanjie
  2019-01-28 13:59   ` Linus Walleij
  2019-01-25  9:59 ` [PATCH RESEND 2/4] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-25  9:59 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199

Delete uart4 and i2c3/4 from JZ4770:
According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
remove it from the JZ4770 code and add a section corresponding the JZ4780.

Fix bugs in i2c0/1:
The pin number was wrong in the original code.

Fix bugs in uart2:
JZ4770 and JZ4780 have different uart2 pins. So the original section JZ4770
has been modified and the corresponding section of JZ4780 has been added.

Fix bugs in mmc0:
JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. So the
original section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in mmc1:
JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original
section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in nemc:
JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original section
JZ4770 has been modified and the corresponding section of JZ4780 has been
added. And add missing cs2~5 groups for JZ4770 and JZ4780.

Fix bugs in cim:
JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original
section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in lcd:
Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/pinctrl/pinctrl-ingenic.c | 249 +++++++++++++++++++++++++++++---------
 1 file changed, 191 insertions(+), 58 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index db6b48e..710062b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -321,23 +321,26 @@ static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
-static int jz4770_uart2_data_pins[] = { 0x66, 0x67, };
-static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
+static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
-static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, };
-static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
-static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
-static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
-static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_nemc_data_pins[] = {
+static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_nemc_8bit_data_pins[] = {
 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 };
+static int jz4770_nemc_16bit_data_pins[] = {
+	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+};
 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
@@ -348,20 +351,21 @@ static int jz4770_nemc_cs3_pins[] = { 0x17, };
 static int jz4770_nemc_cs4_pins[] = { 0x18, };
 static int jz4770_nemc_cs5_pins[] = { 0x19, };
 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
-static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, };
-static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, };
+static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
+static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
-static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, };
-static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, };
-static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, };
-static int jz4770_cim_pins[] = {
-	0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+static int jz4770_cim_8bit_pins[] = {
+	0x26, 0x27, 0x28, 0x29,
+	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4770_cim_12bit_pins[] = {
+	0x32, 0x33, 0xb0, 0xb1,
 };
-static int jz4770_lcd_32bit_pins[] = {
+static int jz4770_lcd_24bit_pins[] = {
 	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
 	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
-	0x58, 0x59, 0x51,
+	0x58, 0x59, 0x5a, 0x5b,
 };
 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
@@ -376,21 +380,22 @@ static int jz4770_uart0_data_funcs[] = { 0, 0, };
 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
 static int jz4770_uart1_data_funcs[] = { 0, 0, };
 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart2_data_funcs[] = { 1, 1, };
-static int jz4770_uart2_hwflow_funcs[] = { 1, 1, };
+static int jz4770_uart2_data_funcs[] = { 0, 0, };
+static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
 static int jz4770_uart3_data_funcs[] = { 0, 1, };
 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart4_data_funcs[] = { 2, 2, };
-static int jz4770_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
-static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
-static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
-static int jz4770_nemc_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
+static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
@@ -404,14 +409,13 @@ static int jz4770_nemc_cs6_funcs[] = { 0, };
 static int jz4770_i2c0_funcs[] = { 0, 0, };
 static int jz4770_i2c1_funcs[] = { 0, 0, };
 static int jz4770_i2c2_funcs[] = { 2, 2, };
-static int jz4770_i2c3_funcs[] = { 1, 1, };
-static int jz4770_i2c4_e_funcs[] = { 1, 1, };
-static int jz4770_i2c4_f_funcs[] = { 1, 1, };
-static int jz4770_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4770_lcd_32bit_funcs[] = {
+static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
+static int jz4770_lcd_24bit_funcs[] = {
+	0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0,
+	0, 0, 0, 0,
 };
 static int jz4770_pwm_pwm0_funcs[] = { 0, };
 static int jz4770_pwm_pwm1_funcs[] = { 0, };
@@ -431,17 +435,18 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
 	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
-	INGENIC_PIN_GROUP("uart4-data", jz4770_uart4_data),
-	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4770_mmc0_8bit_a),
-	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
 	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
-	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
-	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
+	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
-	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
-	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_data),
+	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
+	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
+	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
@@ -455,11 +460,9 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
-	INGENIC_PIN_GROUP("i2c3-data", jz4770_i2c3),
-	INGENIC_PIN_GROUP("i2c4-data-e", jz4770_i2c4_e),
-	INGENIC_PIN_GROUP("i2c4-data-f", jz4770_i2c4_f),
-	INGENIC_PIN_GROUP("cim-data", jz4770_cim),
-	INGENIC_PIN_GROUP("lcd-32bit", jz4770_lcd_32bit),
+	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
+	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
+	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
 	{ "lcd-no-pins", },
 	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
 	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
@@ -475,26 +478,29 @@ static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
-static const char *jz4770_uart4_groups[] = { "uart4-data", };
 static const char *jz4770_mmc0_groups[] = {
-	"mmc0-8bit-a", "mmc0-4bit-a", "mmc0-1bit-a",
-	"mmc0-1bit-e", "mmc0-4bit-e",
+	"mmc0-1bit-a", "mmc0-4bit-a",
+	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
 };
 static const char *jz4770_mmc1_groups[] = {
-	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
+	"mmc1-1bit-d", "mmc1-4bit-d",
+	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 };
 static const char *jz4770_nemc_groups[] = {
-	"nemc-data", "nemc-cle-ale", "nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
+	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
+	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
 };
 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
+static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
+static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
+static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
+static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
-static const char *jz4770_i2c3_groups[] = { "i2c3-data", };
-static const char *jz4770_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
-static const char *jz4770_cim_groups[] = { "cim-data", };
-static const char *jz4770_lcd_groups[] = { "lcd-32bit", "lcd-no-pins", };
+static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
+static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
 static const char *jz4770_pwm0_groups[] = { "pwm0", };
 static const char *jz4770_pwm1_groups[] = { "pwm1", };
 static const char *jz4770_pwm2_groups[] = { "pwm2", };
@@ -509,17 +515,18 @@ static const struct function_desc jz4770_functions[] = {
 	{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
 	{ "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
 	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
-	{ "uart4", jz4770_uart4_groups, ARRAY_SIZE(jz4770_uart4_groups), },
 	{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
 	{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
 	{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
+	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
+	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
+	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
+	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
 	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
 	{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
 	{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
 	{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
-	{ "i2c3", jz4770_i2c3_groups, ARRAY_SIZE(jz4770_i2c3_groups), },
-	{ "i2c4", jz4770_i2c4_groups, ARRAY_SIZE(jz4770_i2c4_groups), },
 	{ "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
 	{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
 	{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
@@ -542,6 +549,130 @@ static const struct ingenic_chip_info jz4770_chip_info = {
 	.pull_downs = jz4770_pull_downs,
 };
 
+static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
+static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
+static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
+static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
+static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
+static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
+
+static int jz4780_uart2_data_funcs[] = { 1, 1, };
+static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
+static int jz4780_uart4_data_funcs[] = { 2, 2, };
+static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
+static int jz4780_i2c3_funcs[] = { 1, 1, };
+static int jz4780_i2c4_e_funcs[] = { 1, 1, };
+static int jz4780_i2c4_f_funcs[] = { 1, 1, };
+
+static const struct group_desc jz4780_groups[] = {
+	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
+	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
+	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
+	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
+	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
+	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
+	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
+	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
+	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
+	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
+	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
+	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
+	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
+	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
+	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
+	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
+	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
+	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
+	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
+	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
+	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
+	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
+	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
+	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
+	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
+	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
+	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
+	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
+	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
+	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
+	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
+	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
+	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
+	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
+	{ "lcd-no-pins", },
+	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
+	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
+	INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
+	INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
+	INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
+	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
+	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
+	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+};
+
+static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
+static const char *jz4780_uart4_groups[] = { "uart4-data", };
+static const char *jz4780_mmc0_groups[] = {
+	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
+	"mmc0-1bit-e", "mmc0-4bit-e",
+};
+static const char *jz4780_mmc1_groups[] = {
+	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
+};
+static const char *jz4780_nemc_groups[] = {
+	"nemc-data", "nemc-cle-ale", "nemc-addr",
+	"nemc-rd-we", "nemc-frd-fwe",
+};
+static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
+static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
+static const char *jz4780_cim_groups[] = { "cim-data", };
+
+static const struct function_desc jz4780_functions[] = {
+	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
+	{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
+	{ "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
+	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
+	{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
+	{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
+	{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
+	{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
+	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
+	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
+	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
+	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
+	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
+	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
+	{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
+	{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
+	{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
+	{ "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
+	{ "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
+	{ "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
+	{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
+	{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
+	{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
+	{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
+	{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
+	{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
+	{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
+	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
+	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+};
+
+static const struct ingenic_chip_info jz4780_chip_info = {
+	.num_chips = 6,
+	.groups = jz4780_groups,
+	.num_groups = ARRAY_SIZE(jz4780_groups),
+	.functions = jz4780_functions,
+	.num_functions = ARRAY_SIZE(jz4780_functions),
+	.pull_ups = jz4770_pull_ups,
+	.pull_downs = jz4770_pull_downs,
+};
+
 static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 {
 	unsigned int val;
@@ -1185,7 +1316,9 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
 	else
 		jzpc->version = (enum jz_version)id->driver_data;
 
-	if (jzpc->version >= ID_JZ4770)
+	if (jzpc->version >= ID_JZ4780)
+		chip_info = &jz4780_chip_info;
+	else if (jzpc->version >= ID_JZ4770)
 		chip_info = &jz4770_chip_info;
 	else if (jzpc->version >= ID_JZ4725B)
 		chip_info = &jz4725b_chip_info;
-- 
2.7.4



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH RESEND 2/4] Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.
  2019-01-25  9:59 Ingenic pinctrl fixes Zhou Yanjie
  2019-01-25  9:59 ` [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
@ 2019-01-25  9:59 ` " Zhou Yanjie
  2019-01-25  9:59 ` [PATCH RESEND 3/4] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-25  9:59 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199

Add mmc2 for JZ4770 and JZ4780:
According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
part of the original code is missing. It is worth noting that JZ4770's
mmc2 supports 8bit mode while JZ4780's does not, so we added the
corresponding code for both models.

Add nemc-wait for JZ4770 and JZ4780:
Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the
original code is missing.

Add mac for JZ4770:
JZ4770 have a mac. But this part of the original code is missing.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/pinctrl/pinctrl-ingenic.c | 46 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 710062b..6501f35 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -335,6 +335,11 @@ static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
+static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
+static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 static int jz4770_nemc_8bit_data_pins[] = {
 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 };
@@ -345,6 +350,7 @@ static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4770_nemc_wait_pins[] = { 0x1b, };
 static int jz4770_nemc_cs1_pins[] = { 0x15, };
 static int jz4770_nemc_cs2_pins[] = { 0x16, };
 static int jz4770_nemc_cs3_pins[] = { 0x17, };
@@ -375,6 +381,10 @@ static int jz4770_pwm_pwm4_pins[] = { 0x84, };
 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
+static int jz4770_mac_rmii_pins[] = {
+	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
+};
+static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
 
 static int jz4770_uart0_data_funcs[] = { 0, 0, };
 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
@@ -394,12 +404,18 @@ static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
+static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
+static int jz4770_nemc_wait_funcs[] = { 0, };
 static int jz4770_nemc_cs1_funcs[] = { 0, };
 static int jz4770_nemc_cs2_funcs[] = { 0, };
 static int jz4770_nemc_cs3_funcs[] = { 0, };
@@ -425,6 +441,8 @@ static int jz4770_pwm_pwm4_funcs[] = { 0, };
 static int jz4770_pwm_pwm5_funcs[] = { 0, };
 static int jz4770_pwm_pwm6_funcs[] = { 0, };
 static int jz4770_pwm_pwm7_funcs[] = { 0, };
+static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_mac_mii_funcs[] = { 0, 0, };
 
 static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
@@ -445,12 +463,18 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
+	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
+	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
+	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
+	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
+	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
@@ -472,6 +496,8 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
 	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
 	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
+	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
 };
 
 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -486,9 +512,13 @@ static const char *jz4770_mmc1_groups[] = {
 	"mmc1-1bit-d", "mmc1-4bit-d",
 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 };
+static const char *jz4770_mmc2_groups[] = {
+	"mmc2-1bit-b", "mmc2-4bit-b",
+	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
+};
 static const char *jz4770_nemc_groups[] = {
 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
-	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
+	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 };
 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
@@ -509,6 +539,7 @@ static const char *jz4770_pwm4_groups[] = { "pwm4", };
 static const char *jz4770_pwm5_groups[] = { "pwm5", };
 static const char *jz4770_pwm6_groups[] = { "pwm6", };
 static const char *jz4770_pwm7_groups[] = { "pwm7", };
+static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
 
 static const struct function_desc jz4770_functions[] = {
 	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
@@ -517,6 +548,7 @@ static const struct function_desc jz4770_functions[] = {
 	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
 	{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
 	{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
+	{ "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
 	{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
@@ -537,6 +569,7 @@ static const struct function_desc jz4770_functions[] = {
 	{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
 	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
 	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+	{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
 };
 
 static const struct ingenic_chip_info jz4770_chip_info = {
@@ -584,11 +617,16 @@ static const struct group_desc jz4780_groups[] = {
 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
+	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
+	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
+	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
 	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
@@ -623,9 +661,12 @@ static const char *jz4780_mmc0_groups[] = {
 static const char *jz4780_mmc1_groups[] = {
 	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
 };
+static const char *jz4780_mmc2_groups[] = {
+	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
+};
 static const char *jz4780_nemc_groups[] = {
 	"nemc-data", "nemc-cle-ale", "nemc-addr",
-	"nemc-rd-we", "nemc-frd-fwe",
+	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 };
 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
@@ -639,6 +680,7 @@ static const struct function_desc jz4780_functions[] = {
 	{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
 	{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
 	{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
+	{ "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
 	{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
-- 
2.7.4



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH RESEND 3/4] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_".
  2019-01-25  9:59 Ingenic pinctrl fixes Zhou Yanjie
  2019-01-25  9:59 ` [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
  2019-01-25  9:59 ` [PATCH RESEND 2/4] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
@ 2019-01-25  9:59 ` Zhou Yanjie
  2019-01-25  9:59 ` [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration Zhou Yanjie
  2019-01-28 15:19 ` Ingenic pinctrl fixes Zhou Yanjie
  4 siblings, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-25  9:59 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199

In the original code, some function names begin with "ingenic_gpio_",
and some with "gpio_ingenic_". For the sake of uniform style,
all of them are changed to the beginning of "ingenic_gpio_".

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/pinctrl/pinctrl-ingenic.c | 46 +++++++++++++++++++--------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 6501f35..2b3f7e4 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -715,7 +715,7 @@ static const struct ingenic_chip_info jz4780_chip_info = {
 	.pull_downs = jz4770_pull_downs,
 };
 
-static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
+static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 {
 	unsigned int val;
 
@@ -724,7 +724,7 @@ static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 	return (u32) val;
 }
 
-static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
+static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
 		u8 reg, u8 offset, bool set)
 {
 	if (set)
@@ -738,7 +738,7 @@ static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
 					  u8 offset)
 {
-	unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
+	unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
 
 	return !!(val & BIT(offset));
 }
@@ -747,9 +747,9 @@ static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
 				   u8 offset, int value)
 {
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
 }
 
 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
@@ -767,21 +767,21 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
 
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, true);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, true);
 		break;
 	case IRQ_TYPE_LEVEL_HIGH:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, false);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
 	default:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, false);
 		break;
 	}
 }
@@ -791,7 +791,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd)
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-	gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
+	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
 }
 
 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
@@ -799,7 +799,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-	gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
+	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
 }
 
 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
@@ -809,9 +809,9 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
 	int irq = irqd->hwirq;
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
 
 	ingenic_gpio_irq_unmask(irqd);
 }
@@ -825,9 +825,9 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
 	ingenic_gpio_irq_mask(irqd);
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
 }
 
 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
@@ -850,9 +850,9 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd)
 	}
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
 }
 
 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -907,9 +907,9 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
 	chained_irq_enter(irq_chip, desc);
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
+		flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
 	else
-		flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
+		flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
 
 	for_each_set_bit(i, &flag, 32)
 		generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
-- 
2.7.4



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration.
  2019-01-25  9:59 Ingenic pinctrl fixes Zhou Yanjie
                   ` (2 preceding siblings ...)
  2019-01-25  9:59 ` [PATCH RESEND 3/4] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
@ 2019-01-25  9:59 ` Zhou Yanjie
  2019-01-25 17:59   ` Paul Cercueil
  2019-01-28 15:19 ` Ingenic pinctrl fixes Zhou Yanjie
  4 siblings, 1 reply; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-25  9:59 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199

Warning is reported when checkpatch indicates that
"static const char * array" should be changed to
"static const char * const".

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
 drivers/pinctrl/pinctrl-ingenic.c | 136 +++++++++++++++++++++-----------------
 1 file changed, 76 insertions(+), 60 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 2b3f7e4..e982896 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -172,23 +172,25 @@ static const struct group_desc jz4740_groups[] = {
 	INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
 };
 
-static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
-static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
-static const char *jz4740_uart1_groups[] = { "uart1-data", };
-static const char *jz4740_lcd_groups[] = {
+static const char * const jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
+static const char * const jz4740_uart0_groups[] = {
+	"uart0-data", "uart0-hwflow",
+};
+static const char * const jz4740_uart1_groups[] = { "uart1-data", };
+static const char * const jz4740_lcd_groups[] = {
 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
 };
-static const char *jz4740_nand_groups[] = {
+static const char * const jz4740_nand_groups[] = {
 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 };
-static const char *jz4740_pwm0_groups[] = { "pwm0", };
-static const char *jz4740_pwm1_groups[] = { "pwm1", };
-static const char *jz4740_pwm2_groups[] = { "pwm2", };
-static const char *jz4740_pwm3_groups[] = { "pwm3", };
-static const char *jz4740_pwm4_groups[] = { "pwm4", };
-static const char *jz4740_pwm5_groups[] = { "pwm5", };
-static const char *jz4740_pwm6_groups[] = { "pwm6", };
-static const char *jz4740_pwm7_groups[] = { "pwm7", };
+static const char * const jz4740_pwm0_groups[] = { "pwm0", };
+static const char * const jz4740_pwm1_groups[] = { "pwm1", };
+static const char * const jz4740_pwm2_groups[] = { "pwm2", };
+static const char * const jz4740_pwm3_groups[] = { "pwm3", };
+static const char * const jz4740_pwm4_groups[] = { "pwm4", };
+static const char * const jz4740_pwm5_groups[] = { "pwm5", };
+static const char * const jz4740_pwm6_groups[] = { "pwm6", };
+static const char * const jz4740_pwm7_groups[] = { "pwm7", };
 
 static const struct function_desc jz4740_functions[] = {
 	{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
@@ -272,19 +274,19 @@ static const struct group_desc jz4725b_groups[] = {
 	INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
 };
 
-static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
-static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
-static const char *jz4725b_uart_groups[] = { "uart-data", };
-static const char *jz4725b_nand_groups[] = {
+static const char * const jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
+static const char * const jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
+static const char * const jz4725b_uart_groups[] = { "uart-data", };
+static const char * const jz4725b_nand_groups[] = {
 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 	"nand-cle-ale", "nand-fre-fwe",
 };
-static const char *jz4725b_pwm0_groups[] = { "pwm0", };
-static const char *jz4725b_pwm1_groups[] = { "pwm1", };
-static const char *jz4725b_pwm2_groups[] = { "pwm2", };
-static const char *jz4725b_pwm3_groups[] = { "pwm3", };
-static const char *jz4725b_pwm4_groups[] = { "pwm4", };
-static const char *jz4725b_pwm5_groups[] = { "pwm5", };
+static const char * const jz4725b_pwm0_groups[] = { "pwm0", };
+static const char * const jz4725b_pwm1_groups[] = { "pwm1", };
+static const char * const jz4725b_pwm2_groups[] = { "pwm2", };
+static const char * const jz4725b_pwm3_groups[] = { "pwm3", };
+static const char * const jz4725b_pwm4_groups[] = { "pwm4", };
+static const char * const jz4725b_pwm5_groups[] = { "pwm5", };
 
 static const struct function_desc jz4725b_functions[] = {
 	{ "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
@@ -500,46 +502,56 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
 };
 
-static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
-static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
-static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
-static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
-static const char *jz4770_mmc0_groups[] = {
+static const char * const jz4770_uart0_groups[] = {
+	"uart0-data", "uart0-hwflow",
+};
+static const char * const jz4770_uart1_groups[] = {
+	"uart1-data", "uart1-hwflow",
+};
+static const char * const jz4770_uart2_groups[] = {
+	"uart2-data", "uart2-hwflow",
+};
+static const char * const jz4770_uart3_groups[] = {
+	"uart3-data", "uart3-hwflow",
+};
+static const char * const jz4770_mmc0_groups[] = {
 	"mmc0-1bit-a", "mmc0-4bit-a",
 	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
 };
-static const char *jz4770_mmc1_groups[] = {
+static const char * const jz4770_mmc1_groups[] = {
 	"mmc1-1bit-d", "mmc1-4bit-d",
 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 };
-static const char *jz4770_mmc2_groups[] = {
+static const char * const jz4770_mmc2_groups[] = {
 	"mmc2-1bit-b", "mmc2-4bit-b",
 	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
 };
-static const char *jz4770_nemc_groups[] = {
+static const char * const jz4770_nemc_groups[] = {
 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 };
-static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
-static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
-static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
-static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
-static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
-static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
-static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
-static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
-static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
-static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
-static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
-static const char *jz4770_pwm0_groups[] = { "pwm0", };
-static const char *jz4770_pwm1_groups[] = { "pwm1", };
-static const char *jz4770_pwm2_groups[] = { "pwm2", };
-static const char *jz4770_pwm3_groups[] = { "pwm3", };
-static const char *jz4770_pwm4_groups[] = { "pwm4", };
-static const char *jz4770_pwm5_groups[] = { "pwm5", };
-static const char *jz4770_pwm6_groups[] = { "pwm6", };
-static const char *jz4770_pwm7_groups[] = { "pwm7", };
-static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
+static const char * const jz4770_cs1_groups[] = { "nemc-cs1", };
+static const char * const jz4770_cs2_groups[] = { "nemc-cs2", };
+static const char * const jz4770_cs3_groups[] = { "nemc-cs3", };
+static const char * const jz4770_cs4_groups[] = { "nemc-cs4", };
+static const char * const jz4770_cs5_groups[] = { "nemc-cs5", };
+static const char * const jz4770_cs6_groups[] = { "nemc-cs6", };
+static const char * const jz4770_i2c0_groups[] = { "i2c0-data", };
+static const char * const jz4770_i2c1_groups[] = { "i2c1-data", };
+static const char * const jz4770_i2c2_groups[] = { "i2c2-data", };
+static const char * const jz4770_cim_groups[] = {
+	"cim-data-8bit", "cim-data-12bit",
+};
+static const char * const jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
+static const char * const jz4770_pwm0_groups[] = { "pwm0", };
+static const char * const jz4770_pwm1_groups[] = { "pwm1", };
+static const char * const jz4770_pwm2_groups[] = { "pwm2", };
+static const char * const jz4770_pwm3_groups[] = { "pwm3", };
+static const char * const jz4770_pwm4_groups[] = { "pwm4", };
+static const char * const jz4770_pwm5_groups[] = { "pwm5", };
+static const char * const jz4770_pwm6_groups[] = { "pwm6", };
+static const char * const jz4770_pwm7_groups[] = { "pwm7", };
+static const char * const jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
 
 static const struct function_desc jz4770_functions[] = {
 	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
@@ -652,25 +664,29 @@ static const struct group_desc jz4780_groups[] = {
 	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
 };
 
-static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
-static const char *jz4780_uart4_groups[] = { "uart4-data", };
-static const char *jz4780_mmc0_groups[] = {
+static const char * const jz4780_uart2_groups[] = {
+	"uart2-data", "uart2-hwflow",
+};
+static const char * const jz4780_uart4_groups[] = { "uart4-data", };
+static const char * const jz4780_mmc0_groups[] = {
 	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
 	"mmc0-1bit-e", "mmc0-4bit-e",
 };
-static const char *jz4780_mmc1_groups[] = {
+static const char * const jz4780_mmc1_groups[] = {
 	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
 };
-static const char *jz4780_mmc2_groups[] = {
+static const char * const jz4780_mmc2_groups[] = {
 	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
 };
-static const char *jz4780_nemc_groups[] = {
+static const char * const jz4780_nemc_groups[] = {
 	"nemc-data", "nemc-cle-ale", "nemc-addr",
 	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 };
-static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
-static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
-static const char *jz4780_cim_groups[] = { "cim-data", };
+static const char * const jz4780_i2c3_groups[] = { "i2c3-data", };
+static const char * const jz4780_i2c4_groups[] = {
+	"i2c4-data-e", "i2c4-data-f",
+};
+static const char * const jz4780_cim_groups[] = { "cim-data", };
 
 static const struct function_desc jz4780_functions[] = {
 	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
-- 
2.7.4



^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration.
  2019-01-25  9:59 ` [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration Zhou Yanjie
@ 2019-01-25 17:59   ` Paul Cercueil
  2019-01-26  8:23     ` Zhou Yanjie
  2019-01-28 19:22     ` Joe Perches
  0 siblings, 2 replies; 22+ messages in thread
From: Paul Cercueil @ 2019-01-25 17:59 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linus.walleij, linux-mips, linux-gpio, linux-kernel, paul.burton,
	syq, jiaxun.yang, 772753199

Hi,

On Fri, Jan 25, 2019 at 6:59 AM, Zhou Yanjie <zhouyanjie@zoho.com> 
wrote:
> Warning is reported when checkpatch indicates that
> "static const char * array" should be changed to
> "static const char * const".
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com 
> <mailto:zhouyanjie@zoho.com>>
> ---
>  drivers/pinctrl/pinctrl-ingenic.c | 136 
> +++++++++++++++++++++-----------------
>  1 file changed, 76 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
> b/drivers/pinctrl/pinctrl-ingenic.c
> index 2b3f7e4..e982896 100644
> --- a/drivers/pinctrl/pinctrl-ingenic.c
> +++ b/drivers/pinctrl/pinctrl-ingenic.c
> @@ -172,23 +172,25 @@ static const struct group_desc jz4740_groups[] 
> = {
>  	INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
>  };
> 
> -static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
> -static const char *jz4740_uart0_groups[] = { "uart0-data", 
> "uart0-hwflow", };
> -static const char *jz4740_uart1_groups[] = { "uart1-data", };
> -static const char *jz4740_lcd_groups[] = {
> +static const char * const jz4740_mmc_groups[] = { "mmc-1bit", 
> "mmc-4bit", };
> +static const char * const jz4740_uart0_groups[] = {
> +	"uart0-data", "uart0-hwflow",
> +};
> +static const char * const jz4740_uart1_groups[] = { "uart1-data", };
> +static const char * const jz4740_lcd_groups[] = {
>  	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", 
> "lcd-no-pins",
>  };
> -static const char *jz4740_nand_groups[] = {
> +static const char * const jz4740_nand_groups[] = {
>  	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
>  };
> -static const char *jz4740_pwm0_groups[] = { "pwm0", };
> -static const char *jz4740_pwm1_groups[] = { "pwm1", };
> -static const char *jz4740_pwm2_groups[] = { "pwm2", };
> -static const char *jz4740_pwm3_groups[] = { "pwm3", };
> -static const char *jz4740_pwm4_groups[] = { "pwm4", };
> -static const char *jz4740_pwm5_groups[] = { "pwm5", };
> -static const char *jz4740_pwm6_groups[] = { "pwm6", };
> -static const char *jz4740_pwm7_groups[] = { "pwm7", };
> +static const char * const jz4740_pwm0_groups[] = { "pwm0", };
> +static const char * const jz4740_pwm1_groups[] = { "pwm1", };
> +static const char * const jz4740_pwm2_groups[] = { "pwm2", };
> +static const char * const jz4740_pwm3_groups[] = { "pwm3", };
> +static const char * const jz4740_pwm4_groups[] = { "pwm4", };
> +static const char * const jz4740_pwm5_groups[] = { "pwm5", };
> +static const char * const jz4740_pwm6_groups[] = { "pwm6", };
> +static const char * const jz4740_pwm7_groups[] = { "pwm7", };
> 
>  static const struct function_desc jz4740_functions[] = {
>  	{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },

With this patch applied I get this:

drivers/pinctrl/pinctrl-ingenic.c:196:11: attention : initialization 
discards
‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
           ^~~~~~~~~~~~~~~~~

> @@ -272,19 +274,19 @@ static const struct group_desc jz4725b_groups[] 
> = {
>  	INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
>  };
> 
> -static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", 
> "mmc0-4bit", };
> -static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", 
> "mmc1-4bit", };
> -static const char *jz4725b_uart_groups[] = { "uart-data", };
> -static const char *jz4725b_nand_groups[] = {
> +static const char * const jz4725b_mmc0_groups[] = { "mmc0-1bit", 
> "mmc0-4bit", };
> +static const char * const jz4725b_mmc1_groups[] = { "mmc1-1bit", 
> "mmc1-4bit", };
> +static const char * const jz4725b_uart_groups[] = { "uart-data", };
> +static const char * const jz4725b_nand_groups[] = {
>  	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
>  	"nand-cle-ale", "nand-fre-fwe",
>  };
> -static const char *jz4725b_pwm0_groups[] = { "pwm0", };
> -static const char *jz4725b_pwm1_groups[] = { "pwm1", };
> -static const char *jz4725b_pwm2_groups[] = { "pwm2", };
> -static const char *jz4725b_pwm3_groups[] = { "pwm3", };
> -static const char *jz4725b_pwm4_groups[] = { "pwm4", };
> -static const char *jz4725b_pwm5_groups[] = { "pwm5", };
> +static const char * const jz4725b_pwm0_groups[] = { "pwm0", };
> +static const char * const jz4725b_pwm1_groups[] = { "pwm1", };
> +static const char * const jz4725b_pwm2_groups[] = { "pwm2", };
> +static const char * const jz4725b_pwm3_groups[] = { "pwm3", };
> +static const char * const jz4725b_pwm4_groups[] = { "pwm4", };
> +static const char * const jz4725b_pwm5_groups[] = { "pwm5", };
> 
>  static const struct function_desc jz4725b_functions[] = {
>  	{ "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
> @@ -500,46 +502,56 @@ static const struct group_desc jz4770_groups[] 
> = {
>  	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
>  };
> 
> -static const char *jz4770_uart0_groups[] = { "uart0-data", 
> "uart0-hwflow", };
> -static const char *jz4770_uart1_groups[] = { "uart1-data", 
> "uart1-hwflow", };
> -static const char *jz4770_uart2_groups[] = { "uart2-data", 
> "uart2-hwflow", };
> -static const char *jz4770_uart3_groups[] = { "uart3-data", 
> "uart3-hwflow", };
> -static const char *jz4770_mmc0_groups[] = {
> +static const char * const jz4770_uart0_groups[] = {
> +	"uart0-data", "uart0-hwflow",
> +};
> +static const char * const jz4770_uart1_groups[] = {
> +	"uart1-data", "uart1-hwflow",
> +};
> +static const char * const jz4770_uart2_groups[] = {
> +	"uart2-data", "uart2-hwflow",
> +};
> +static const char * const jz4770_uart3_groups[] = {
> +	"uart3-data", "uart3-hwflow",
> +};
> +static const char * const jz4770_mmc0_groups[] = {
>  	"mmc0-1bit-a", "mmc0-4bit-a",
>  	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
>  };
> -static const char *jz4770_mmc1_groups[] = {
> +static const char * const jz4770_mmc1_groups[] = {
>  	"mmc1-1bit-d", "mmc1-4bit-d",
>  	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
>  };
> -static const char *jz4770_mmc2_groups[] = {
> +static const char * const jz4770_mmc2_groups[] = {
>  	"mmc2-1bit-b", "mmc2-4bit-b",
>  	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
>  };
> -static const char *jz4770_nemc_groups[] = {
> +static const char * const jz4770_nemc_groups[] = {
>  	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
>  	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
>  };
> -static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
> -static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
> -static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
> -static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
> -static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
> -static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
> -static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
> -static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
> -static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
> -static const char *jz4770_cim_groups[] = { "cim-data-8bit", 
> "cim-data-12bit", };
> -static const char *jz4770_lcd_groups[] = { "lcd-24bit", 
> "lcd-no-pins", };
> -static const char *jz4770_pwm0_groups[] = { "pwm0", };
> -static const char *jz4770_pwm1_groups[] = { "pwm1", };
> -static const char *jz4770_pwm2_groups[] = { "pwm2", };
> -static const char *jz4770_pwm3_groups[] = { "pwm3", };
> -static const char *jz4770_pwm4_groups[] = { "pwm4", };
> -static const char *jz4770_pwm5_groups[] = { "pwm5", };
> -static const char *jz4770_pwm6_groups[] = { "pwm6", };
> -static const char *jz4770_pwm7_groups[] = { "pwm7", };
> -static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
> +static const char * const jz4770_cs1_groups[] = { "nemc-cs1", };
> +static const char * const jz4770_cs2_groups[] = { "nemc-cs2", };
> +static const char * const jz4770_cs3_groups[] = { "nemc-cs3", };
> +static const char * const jz4770_cs4_groups[] = { "nemc-cs4", };
> +static const char * const jz4770_cs5_groups[] = { "nemc-cs5", };
> +static const char * const jz4770_cs6_groups[] = { "nemc-cs6", };
> +static const char * const jz4770_i2c0_groups[] = { "i2c0-data", };
> +static const char * const jz4770_i2c1_groups[] = { "i2c1-data", };
> +static const char * const jz4770_i2c2_groups[] = { "i2c2-data", };
> +static const char * const jz4770_cim_groups[] = {
> +	"cim-data-8bit", "cim-data-12bit",
> +};
> +static const char * const jz4770_lcd_groups[] = { "lcd-24bit", 
> "lcd-no-pins", };
> +static const char * const jz4770_pwm0_groups[] = { "pwm0", };
> +static const char * const jz4770_pwm1_groups[] = { "pwm1", };
> +static const char * const jz4770_pwm2_groups[] = { "pwm2", };
> +static const char * const jz4770_pwm3_groups[] = { "pwm3", };
> +static const char * const jz4770_pwm4_groups[] = { "pwm4", };
> +static const char * const jz4770_pwm5_groups[] = { "pwm5", };
> +static const char * const jz4770_pwm6_groups[] = { "pwm6", };
> +static const char * const jz4770_pwm7_groups[] = { "pwm7", };
> +static const char * const jz4770_mac_groups[] = { "mac-rmii", 
> "mac-mii", };
> 
>  static const struct function_desc jz4770_functions[] = {
>  	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
> @@ -652,25 +664,29 @@ static const struct group_desc jz4780_groups[] 
> = {
>  	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
>  };
> 
> -static const char *jz4780_uart2_groups[] = { "uart2-data", 
> "uart2-hwflow", };
> -static const char *jz4780_uart4_groups[] = { "uart4-data", };
> -static const char *jz4780_mmc0_groups[] = {
> +static const char * const jz4780_uart2_groups[] = {
> +	"uart2-data", "uart2-hwflow",
> +};
> +static const char * const jz4780_uart4_groups[] = { "uart4-data", };
> +static const char * const jz4780_mmc0_groups[] = {
>  	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
>  	"mmc0-1bit-e", "mmc0-4bit-e",
>  };
> -static const char *jz4780_mmc1_groups[] = {
> +static const char * const jz4780_mmc1_groups[] = {
>  	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
>  };
> -static const char *jz4780_mmc2_groups[] = {
> +static const char * const jz4780_mmc2_groups[] = {
>  	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
>  };
> -static const char *jz4780_nemc_groups[] = {
> +static const char * const jz4780_nemc_groups[] = {
>  	"nemc-data", "nemc-cle-ale", "nemc-addr",
>  	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
>  };
> -static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
> -static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", 
> "i2c4-data-f", };
> -static const char *jz4780_cim_groups[] = { "cim-data", };
> +static const char * const jz4780_i2c3_groups[] = { "i2c3-data", };
> +static const char * const jz4780_i2c4_groups[] = {
> +	"i2c4-data-e", "i2c4-data-f",
> +};
> +static const char * const jz4780_cim_groups[] = { "cim-data", };
> 
>  static const struct function_desc jz4780_functions[] = {
>  	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
> --
> 2.7.4
> 
> 



^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration.
  2019-01-25 17:59   ` Paul Cercueil
@ 2019-01-26  8:23     ` Zhou Yanjie
  2019-01-28 19:22     ` Joe Perches
  1 sibling, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-26  8:23 UTC (permalink / raw)
  To: Paul Cercueil
  Cc: linus.walleij, linux-mips, linux-gpio, linux-kernel, paul.burton,
	syq, jiaxun.yang, 772753199, apw, joe

My fault, I checked it again, the reason for this problem is that the
member "pins" in structure "group_desc" is not a const type.
It did not report this warning when I used gcc-5.2.0.
After switching to gcc-6.3.0, the warning appeared.
Should we ignore the warning information given by checkpatch.pl?

On 2019年01月26日 01:59, Paul Cercueil wrote:
> Hi,
>
> On Fri, Jan 25, 2019 at 6:59 AM, Zhou Yanjie <zhouyanjie@zoho.com> wrote:
>> Warning is reported when checkpatch indicates that
>> "static const char * array" should be changed to
>> "static const char * const".
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com 
>> <mailto:zhouyanjie@zoho.com>>
>> ---
>>  drivers/pinctrl/pinctrl-ingenic.c | 136 
>> +++++++++++++++++++++-----------------
>>  1 file changed, 76 insertions(+), 60 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
>> b/drivers/pinctrl/pinctrl-ingenic.c
>> index 2b3f7e4..e982896 100644
>> --- a/drivers/pinctrl/pinctrl-ingenic.c
>> +++ b/drivers/pinctrl/pinctrl-ingenic.c
>> @@ -172,23 +172,25 @@ static const struct group_desc jz4740_groups[] = {
>>      INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
>>  };
>>
>> -static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
>> -static const char *jz4740_uart0_groups[] = { "uart0-data", 
>> "uart0-hwflow", };
>> -static const char *jz4740_uart1_groups[] = { "uart1-data", };
>> -static const char *jz4740_lcd_groups[] = {
>> +static const char * const jz4740_mmc_groups[] = { "mmc-1bit", 
>> "mmc-4bit", };
>> +static const char * const jz4740_uart0_groups[] = {
>> +    "uart0-data", "uart0-hwflow",
>> +};
>> +static const char * const jz4740_uart1_groups[] = { "uart1-data", };
>> +static const char * const jz4740_lcd_groups[] = {
>>      "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", 
>> "lcd-no-pins",
>>  };
>> -static const char *jz4740_nand_groups[] = {
>> +static const char * const jz4740_nand_groups[] = {
>>      "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
>>  };
>> -static const char *jz4740_pwm0_groups[] = { "pwm0", };
>> -static const char *jz4740_pwm1_groups[] = { "pwm1", };
>> -static const char *jz4740_pwm2_groups[] = { "pwm2", };
>> -static const char *jz4740_pwm3_groups[] = { "pwm3", };
>> -static const char *jz4740_pwm4_groups[] = { "pwm4", };
>> -static const char *jz4740_pwm5_groups[] = { "pwm5", };
>> -static const char *jz4740_pwm6_groups[] = { "pwm6", };
>> -static const char *jz4740_pwm7_groups[] = { "pwm7", };
>> +static const char * const jz4740_pwm0_groups[] = { "pwm0", };
>> +static const char * const jz4740_pwm1_groups[] = { "pwm1", };
>> +static const char * const jz4740_pwm2_groups[] = { "pwm2", };
>> +static const char * const jz4740_pwm3_groups[] = { "pwm3", };
>> +static const char * const jz4740_pwm4_groups[] = { "pwm4", };
>> +static const char * const jz4740_pwm5_groups[] = { "pwm5", };
>> +static const char * const jz4740_pwm6_groups[] = { "pwm6", };
>> +static const char * const jz4740_pwm7_groups[] = { "pwm7", };
>>
>>  static const struct function_desc jz4740_functions[] = {
>>      { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
>
> With this patch applied I get this:
>
> drivers/pinctrl/pinctrl-ingenic.c:196:11: attention : initialization 
> discards
> ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
>  { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
>           ^~~~~~~~~~~~~~~~~
>
>> @@ -272,19 +274,19 @@ static const struct group_desc jz4725b_groups[] 
>> = {
>>      INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
>>  };
>>
>> -static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", 
>> "mmc0-4bit", };
>> -static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", 
>> "mmc1-4bit", };
>> -static const char *jz4725b_uart_groups[] = { "uart-data", };
>> -static const char *jz4725b_nand_groups[] = {
>> +static const char * const jz4725b_mmc0_groups[] = { "mmc0-1bit", 
>> "mmc0-4bit", };
>> +static const char * const jz4725b_mmc1_groups[] = { "mmc1-1bit", 
>> "mmc1-4bit", };
>> +static const char * const jz4725b_uart_groups[] = { "uart-data", };
>> +static const char * const jz4725b_nand_groups[] = {
>>      "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
>>      "nand-cle-ale", "nand-fre-fwe",
>>  };
>> -static const char *jz4725b_pwm0_groups[] = { "pwm0", };
>> -static const char *jz4725b_pwm1_groups[] = { "pwm1", };
>> -static const char *jz4725b_pwm2_groups[] = { "pwm2", };
>> -static const char *jz4725b_pwm3_groups[] = { "pwm3", };
>> -static const char *jz4725b_pwm4_groups[] = { "pwm4", };
>> -static const char *jz4725b_pwm5_groups[] = { "pwm5", };
>> +static const char * const jz4725b_pwm0_groups[] = { "pwm0", };
>> +static const char * const jz4725b_pwm1_groups[] = { "pwm1", };
>> +static const char * const jz4725b_pwm2_groups[] = { "pwm2", };
>> +static const char * const jz4725b_pwm3_groups[] = { "pwm3", };
>> +static const char * const jz4725b_pwm4_groups[] = { "pwm4", };
>> +static const char * const jz4725b_pwm5_groups[] = { "pwm5", };
>>
>>  static const struct function_desc jz4725b_functions[] = {
>>      { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
>> @@ -500,46 +502,56 @@ static const struct group_desc jz4770_groups[] = {
>>      INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
>>  };
>>
>> -static const char *jz4770_uart0_groups[] = { "uart0-data", 
>> "uart0-hwflow", };
>> -static const char *jz4770_uart1_groups[] = { "uart1-data", 
>> "uart1-hwflow", };
>> -static const char *jz4770_uart2_groups[] = { "uart2-data", 
>> "uart2-hwflow", };
>> -static const char *jz4770_uart3_groups[] = { "uart3-data", 
>> "uart3-hwflow", };
>> -static const char *jz4770_mmc0_groups[] = {
>> +static const char * const jz4770_uart0_groups[] = {
>> +    "uart0-data", "uart0-hwflow",
>> +};
>> +static const char * const jz4770_uart1_groups[] = {
>> +    "uart1-data", "uart1-hwflow",
>> +};
>> +static const char * const jz4770_uart2_groups[] = {
>> +    "uart2-data", "uart2-hwflow",
>> +};
>> +static const char * const jz4770_uart3_groups[] = {
>> +    "uart3-data", "uart3-hwflow",
>> +};
>> +static const char * const jz4770_mmc0_groups[] = {
>>      "mmc0-1bit-a", "mmc0-4bit-a",
>>      "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
>>  };
>> -static const char *jz4770_mmc1_groups[] = {
>> +static const char * const jz4770_mmc1_groups[] = {
>>      "mmc1-1bit-d", "mmc1-4bit-d",
>>      "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
>>  };
>> -static const char *jz4770_mmc2_groups[] = {
>> +static const char * const jz4770_mmc2_groups[] = {
>>      "mmc2-1bit-b", "mmc2-4bit-b",
>>      "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
>>  };
>> -static const char *jz4770_nemc_groups[] = {
>> +static const char * const jz4770_nemc_groups[] = {
>>      "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
>>      "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
>>  };
>> -static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
>> -static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
>> -static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
>> -static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
>> -static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
>> -static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
>> -static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
>> -static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
>> -static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
>> -static const char *jz4770_cim_groups[] = { "cim-data-8bit", 
>> "cim-data-12bit", };
>> -static const char *jz4770_lcd_groups[] = { "lcd-24bit", 
>> "lcd-no-pins", };
>> -static const char *jz4770_pwm0_groups[] = { "pwm0", };
>> -static const char *jz4770_pwm1_groups[] = { "pwm1", };
>> -static const char *jz4770_pwm2_groups[] = { "pwm2", };
>> -static const char *jz4770_pwm3_groups[] = { "pwm3", };
>> -static const char *jz4770_pwm4_groups[] = { "pwm4", };
>> -static const char *jz4770_pwm5_groups[] = { "pwm5", };
>> -static const char *jz4770_pwm6_groups[] = { "pwm6", };
>> -static const char *jz4770_pwm7_groups[] = { "pwm7", };
>> -static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
>> +static const char * const jz4770_cs1_groups[] = { "nemc-cs1", };
>> +static const char * const jz4770_cs2_groups[] = { "nemc-cs2", };
>> +static const char * const jz4770_cs3_groups[] = { "nemc-cs3", };
>> +static const char * const jz4770_cs4_groups[] = { "nemc-cs4", };
>> +static const char * const jz4770_cs5_groups[] = { "nemc-cs5", };
>> +static const char * const jz4770_cs6_groups[] = { "nemc-cs6", };
>> +static const char * const jz4770_i2c0_groups[] = { "i2c0-data", };
>> +static const char * const jz4770_i2c1_groups[] = { "i2c1-data", };
>> +static const char * const jz4770_i2c2_groups[] = { "i2c2-data", };
>> +static const char * const jz4770_cim_groups[] = {
>> +    "cim-data-8bit", "cim-data-12bit",
>> +};
>> +static const char * const jz4770_lcd_groups[] = { "lcd-24bit", 
>> "lcd-no-pins", };
>> +static const char * const jz4770_pwm0_groups[] = { "pwm0", };
>> +static const char * const jz4770_pwm1_groups[] = { "pwm1", };
>> +static const char * const jz4770_pwm2_groups[] = { "pwm2", };
>> +static const char * const jz4770_pwm3_groups[] = { "pwm3", };
>> +static const char * const jz4770_pwm4_groups[] = { "pwm4", };
>> +static const char * const jz4770_pwm5_groups[] = { "pwm5", };
>> +static const char * const jz4770_pwm6_groups[] = { "pwm6", };
>> +static const char * const jz4770_pwm7_groups[] = { "pwm7", };
>> +static const char * const jz4770_mac_groups[] = { "mac-rmii", 
>> "mac-mii", };
>>
>>  static const struct function_desc jz4770_functions[] = {
>>      { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
>> @@ -652,25 +664,29 @@ static const struct group_desc jz4780_groups[] = {
>>      INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
>>  };
>>
>> -static const char *jz4780_uart2_groups[] = { "uart2-data", 
>> "uart2-hwflow", };
>> -static const char *jz4780_uart4_groups[] = { "uart4-data", };
>> -static const char *jz4780_mmc0_groups[] = {
>> +static const char * const jz4780_uart2_groups[] = {
>> +    "uart2-data", "uart2-hwflow",
>> +};
>> +static const char * const jz4780_uart4_groups[] = { "uart4-data", };
>> +static const char * const jz4780_mmc0_groups[] = {
>>      "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
>>      "mmc0-1bit-e", "mmc0-4bit-e",
>>  };
>> -static const char *jz4780_mmc1_groups[] = {
>> +static const char * const jz4780_mmc1_groups[] = {
>>      "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
>>  };
>> -static const char *jz4780_mmc2_groups[] = {
>> +static const char * const jz4780_mmc2_groups[] = {
>>      "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
>>  };
>> -static const char *jz4780_nemc_groups[] = {
>> +static const char * const jz4780_nemc_groups[] = {
>>      "nemc-data", "nemc-cle-ale", "nemc-addr",
>>      "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
>>  };
>> -static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
>> -static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", 
>> "i2c4-data-f", };
>> -static const char *jz4780_cim_groups[] = { "cim-data", };
>> +static const char * const jz4780_i2c3_groups[] = { "i2c3-data", };
>> +static const char * const jz4780_i2c4_groups[] = {
>> +    "i2c4-data-e", "i2c4-data-f",
>> +};
>> +static const char * const jz4780_cim_groups[] = { "cim-data", };
>>
>>  static const struct function_desc jz4780_functions[] = {
>>      { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
>> -- 
>> 2.7.4
>>
>>
>
>




^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.
  2019-01-25  9:59 ` [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
@ 2019-01-28 13:59   ` Linus Walleij
  2019-01-28 14:42     ` Zhou Yanjie
  0 siblings, 1 reply; 22+ messages in thread
From: Linus Walleij @ 2019-01-28 13:59 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, open list:GPIO SUBSYSTEM, linux-kernel, Paul Burton,
	Paul Cercueil, syq, Jiaxun Yang, 772753199

This series looks good to me, but it would be nice if you could
fix the warning pointed out by Paul, and I would also
like some ACK from Paul C on the patches so I know this is
fine with him.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.
  2019-01-28 13:59   ` Linus Walleij
@ 2019-01-28 14:42     ` Zhou Yanjie
  2019-01-28 14:47       ` Linus Walleij
  0 siblings, 1 reply; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-28 14:42 UTC (permalink / raw)
  To: Linus Walleij
  Cc: linux-mips, open list:GPIO SUBSYSTEM, linux-kernel, Paul Burton,
	Paul Cercueil, syq, Jiaxun Yang, 772753199

Thank you for your reply. I am working on v2, and I have removed the 
fourth patch in v2,
so there will be no warnings at compile time. But this will cause some 
warning messages
when checkpatch, I am confused whether I can ignore these warnings.

On 2019年01月28日 21:59, Linus Walleij wrote:
> This series looks good to me, but it would be nice if you could
> fix the warning pointed out by Paul, and I would also
> like some ACK from Paul C on the patches so I know this is
> fine with him.
>
> Yours,
> Linus Walleij




^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.
  2019-01-28 14:42     ` Zhou Yanjie
@ 2019-01-28 14:47       ` Linus Walleij
  0 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2019-01-28 14:47 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, open list:GPIO SUBSYSTEM, linux-kernel, Paul Burton,
	Paul Cercueil, syq, Jiaxun Yang, 772753199

On Mon, Jan 28, 2019 at 3:43 PM Zhou Yanjie <zhouyanjie@zoho.com> wrote:

> Thank you for your reply. I am working on v2, and I have removed the
> fourth patch in v2,
> so there will be no warnings at compile time. But this will cause some
> warning messages
> when checkpatch, I am confused whether I can ignore these warnings.

I don't care super much about checkpatch warnings, compiler
warnings for const correctness is more important.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Ingenic pinctrl fixes.
  2019-01-25  9:59 Ingenic pinctrl fixes Zhou Yanjie
                   ` (3 preceding siblings ...)
  2019-01-25  9:59 ` [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration Zhou Yanjie
@ 2019-01-28 15:19 ` Zhou Yanjie
  2019-01-28 15:19   ` [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
                     ` (2 more replies)
  4 siblings, 3 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-28 15:19 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199

Fix compile-time warnings.



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.
  2019-01-28 15:19 ` Ingenic pinctrl fixes Zhou Yanjie
@ 2019-01-28 15:19   ` Zhou Yanjie
  2019-01-28 18:17     ` Paul Cercueil
  2019-01-30  9:28     ` Linus Walleij
  2019-01-28 15:19   ` [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
  2019-01-28 15:19   ` [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
  2 siblings, 2 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-28 15:19 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199, Zhou Yanjie

From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Delete uart4 and i2c3/4 from JZ4770:
According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
remove it from the JZ4770 code and add a section corresponding the JZ4780.

Fix bugs in i2c0/1:
The pin number was wrong in the original code.

Fix bugs in uart2:
JZ4770 and JZ4780 have different uart2 pins. So the original section JZ4770
has been modified and the corresponding section of JZ4780 has been added.

Fix bugs in mmc0:
JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. So the
original section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in mmc1:
JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original
section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in nemc:
JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original section
JZ4770 has been modified and the corresponding section of JZ4780 has been
added. And add missing cs2~5 groups for JZ4770 and JZ4780.

Fix bugs in cim:
JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original
section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in lcd:
Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit.

Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
---
 drivers/pinctrl/pinctrl-ingenic.c | 249 +++++++++++++++++++++++++++++---------
 1 file changed, 191 insertions(+), 58 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index db6b48e..710062b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -321,23 +321,26 @@ static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
-static int jz4770_uart2_data_pins[] = { 0x66, 0x67, };
-static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
+static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
-static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, };
-static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
-static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
-static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
-static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_nemc_data_pins[] = {
+static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_nemc_8bit_data_pins[] = {
 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 };
+static int jz4770_nemc_16bit_data_pins[] = {
+	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+};
 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
@@ -348,20 +351,21 @@ static int jz4770_nemc_cs3_pins[] = { 0x17, };
 static int jz4770_nemc_cs4_pins[] = { 0x18, };
 static int jz4770_nemc_cs5_pins[] = { 0x19, };
 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
-static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, };
-static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, };
+static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
+static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
-static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, };
-static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, };
-static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, };
-static int jz4770_cim_pins[] = {
-	0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+static int jz4770_cim_8bit_pins[] = {
+	0x26, 0x27, 0x28, 0x29,
+	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4770_cim_12bit_pins[] = {
+	0x32, 0x33, 0xb0, 0xb1,
 };
-static int jz4770_lcd_32bit_pins[] = {
+static int jz4770_lcd_24bit_pins[] = {
 	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
 	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
-	0x58, 0x59, 0x51,
+	0x58, 0x59, 0x5a, 0x5b,
 };
 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
@@ -376,21 +380,22 @@ static int jz4770_uart0_data_funcs[] = { 0, 0, };
 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
 static int jz4770_uart1_data_funcs[] = { 0, 0, };
 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart2_data_funcs[] = { 1, 1, };
-static int jz4770_uart2_hwflow_funcs[] = { 1, 1, };
+static int jz4770_uart2_data_funcs[] = { 0, 0, };
+static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
 static int jz4770_uart3_data_funcs[] = { 0, 1, };
 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
-static int jz4770_uart4_data_funcs[] = { 2, 2, };
-static int jz4770_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
-static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
-static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
-static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
-static int jz4770_nemc_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
+static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
+static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
@@ -404,14 +409,13 @@ static int jz4770_nemc_cs6_funcs[] = { 0, };
 static int jz4770_i2c0_funcs[] = { 0, 0, };
 static int jz4770_i2c1_funcs[] = { 0, 0, };
 static int jz4770_i2c2_funcs[] = { 2, 2, };
-static int jz4770_i2c3_funcs[] = { 1, 1, };
-static int jz4770_i2c4_e_funcs[] = { 1, 1, };
-static int jz4770_i2c4_f_funcs[] = { 1, 1, };
-static int jz4770_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
-static int jz4770_lcd_32bit_funcs[] = {
+static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
+static int jz4770_lcd_24bit_funcs[] = {
+	0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0,
+	0, 0, 0, 0,
 };
 static int jz4770_pwm_pwm0_funcs[] = { 0, };
 static int jz4770_pwm_pwm1_funcs[] = { 0, };
@@ -431,17 +435,18 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
 	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
-	INGENIC_PIN_GROUP("uart4-data", jz4770_uart4_data),
-	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4770_mmc0_8bit_a),
-	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
 	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
-	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
-	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
+	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
-	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
-	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_data),
+	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
+	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
+	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
@@ -455,11 +460,9 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
-	INGENIC_PIN_GROUP("i2c3-data", jz4770_i2c3),
-	INGENIC_PIN_GROUP("i2c4-data-e", jz4770_i2c4_e),
-	INGENIC_PIN_GROUP("i2c4-data-f", jz4770_i2c4_f),
-	INGENIC_PIN_GROUP("cim-data", jz4770_cim),
-	INGENIC_PIN_GROUP("lcd-32bit", jz4770_lcd_32bit),
+	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
+	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
+	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
 	{ "lcd-no-pins", },
 	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
 	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
@@ -475,26 +478,29 @@ static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
-static const char *jz4770_uart4_groups[] = { "uart4-data", };
 static const char *jz4770_mmc0_groups[] = {
-	"mmc0-8bit-a", "mmc0-4bit-a", "mmc0-1bit-a",
-	"mmc0-1bit-e", "mmc0-4bit-e",
+	"mmc0-1bit-a", "mmc0-4bit-a",
+	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
 };
 static const char *jz4770_mmc1_groups[] = {
-	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
+	"mmc1-1bit-d", "mmc1-4bit-d",
+	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 };
 static const char *jz4770_nemc_groups[] = {
-	"nemc-data", "nemc-cle-ale", "nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
+	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
+	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
 };
 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
+static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
+static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
+static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
+static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
-static const char *jz4770_i2c3_groups[] = { "i2c3-data", };
-static const char *jz4770_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
-static const char *jz4770_cim_groups[] = { "cim-data", };
-static const char *jz4770_lcd_groups[] = { "lcd-32bit", "lcd-no-pins", };
+static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
+static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
 static const char *jz4770_pwm0_groups[] = { "pwm0", };
 static const char *jz4770_pwm1_groups[] = { "pwm1", };
 static const char *jz4770_pwm2_groups[] = { "pwm2", };
@@ -509,17 +515,18 @@ static const struct function_desc jz4770_functions[] = {
 	{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
 	{ "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
 	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
-	{ "uart4", jz4770_uart4_groups, ARRAY_SIZE(jz4770_uart4_groups), },
 	{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
 	{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
 	{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
+	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
+	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
+	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
+	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
 	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
 	{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
 	{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
 	{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
-	{ "i2c3", jz4770_i2c3_groups, ARRAY_SIZE(jz4770_i2c3_groups), },
-	{ "i2c4", jz4770_i2c4_groups, ARRAY_SIZE(jz4770_i2c4_groups), },
 	{ "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
 	{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
 	{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
@@ -542,6 +549,130 @@ static const struct ingenic_chip_info jz4770_chip_info = {
 	.pull_downs = jz4770_pull_downs,
 };
 
+static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
+static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
+static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
+static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
+static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
+static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
+
+static int jz4780_uart2_data_funcs[] = { 1, 1, };
+static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
+static int jz4780_uart4_data_funcs[] = { 2, 2, };
+static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
+static int jz4780_i2c3_funcs[] = { 1, 1, };
+static int jz4780_i2c4_e_funcs[] = { 1, 1, };
+static int jz4780_i2c4_f_funcs[] = { 1, 1, };
+
+static const struct group_desc jz4780_groups[] = {
+	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
+	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
+	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
+	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
+	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
+	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
+	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
+	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
+	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
+	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
+	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
+	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
+	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
+	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
+	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
+	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
+	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
+	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
+	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
+	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
+	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
+	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
+	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
+	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
+	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
+	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
+	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
+	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
+	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
+	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
+	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
+	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
+	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
+	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
+	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
+	{ "lcd-no-pins", },
+	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
+	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
+	INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
+	INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
+	INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
+	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
+	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
+	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+};
+
+static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
+static const char *jz4780_uart4_groups[] = { "uart4-data", };
+static const char *jz4780_mmc0_groups[] = {
+	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
+	"mmc0-1bit-e", "mmc0-4bit-e",
+};
+static const char *jz4780_mmc1_groups[] = {
+	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
+};
+static const char *jz4780_nemc_groups[] = {
+	"nemc-data", "nemc-cle-ale", "nemc-addr",
+	"nemc-rd-we", "nemc-frd-fwe",
+};
+static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
+static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
+static const char *jz4780_cim_groups[] = { "cim-data", };
+
+static const struct function_desc jz4780_functions[] = {
+	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
+	{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
+	{ "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
+	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
+	{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
+	{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
+	{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
+	{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
+	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
+	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
+	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
+	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
+	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
+	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
+	{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
+	{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
+	{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
+	{ "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
+	{ "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
+	{ "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
+	{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
+	{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
+	{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
+	{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
+	{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
+	{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
+	{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
+	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
+	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+};
+
+static const struct ingenic_chip_info jz4780_chip_info = {
+	.num_chips = 6,
+	.groups = jz4780_groups,
+	.num_groups = ARRAY_SIZE(jz4780_groups),
+	.functions = jz4780_functions,
+	.num_functions = ARRAY_SIZE(jz4780_functions),
+	.pull_ups = jz4770_pull_ups,
+	.pull_downs = jz4770_pull_downs,
+};
+
 static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 {
 	unsigned int val;
@@ -1185,7 +1316,9 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
 	else
 		jzpc->version = (enum jz_version)id->driver_data;
 
-	if (jzpc->version >= ID_JZ4770)
+	if (jzpc->version >= ID_JZ4780)
+		chip_info = &jz4780_chip_info;
+	else if (jzpc->version >= ID_JZ4770)
 		chip_info = &jz4770_chip_info;
 	else if (jzpc->version >= ID_JZ4725B)
 		chip_info = &jz4725b_chip_info;
-- 
2.7.4



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.
  2019-01-28 15:19 ` Ingenic pinctrl fixes Zhou Yanjie
  2019-01-28 15:19   ` [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
@ 2019-01-28 15:19   ` " Zhou Yanjie
  2019-01-28 18:13     ` Paul Cercueil
  2019-01-30  9:30     ` Linus Walleij
  2019-01-28 15:19   ` [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
  2 siblings, 2 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-28 15:19 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199, Zhou Yanjie

From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Add mmc2 for JZ4770 and JZ4780:
According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
part of the original code is missing. It is worth noting that JZ4770's
mmc2 supports 8bit mode while JZ4780's does not, so we added the
corresponding code for both models.

Add nemc-wait for JZ4770 and JZ4780:
Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the
original code is missing.

Add mac for JZ4770:
JZ4770 have a mac. But this part of the original code is missing.

Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
---
 drivers/pinctrl/pinctrl-ingenic.c | 46 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 710062b..6501f35 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -335,6 +335,11 @@ static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
+static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
+static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 static int jz4770_nemc_8bit_data_pins[] = {
 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 };
@@ -345,6 +350,7 @@ static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4770_nemc_wait_pins[] = { 0x1b, };
 static int jz4770_nemc_cs1_pins[] = { 0x15, };
 static int jz4770_nemc_cs2_pins[] = { 0x16, };
 static int jz4770_nemc_cs3_pins[] = { 0x17, };
@@ -375,6 +381,10 @@ static int jz4770_pwm_pwm4_pins[] = { 0x84, };
 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
+static int jz4770_mac_rmii_pins[] = {
+	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
+};
+static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
 
 static int jz4770_uart0_data_funcs[] = { 0, 0, };
 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
@@ -394,12 +404,18 @@ static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
+static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
+static int jz4770_nemc_wait_funcs[] = { 0, };
 static int jz4770_nemc_cs1_funcs[] = { 0, };
 static int jz4770_nemc_cs2_funcs[] = { 0, };
 static int jz4770_nemc_cs3_funcs[] = { 0, };
@@ -425,6 +441,8 @@ static int jz4770_pwm_pwm4_funcs[] = { 0, };
 static int jz4770_pwm_pwm5_funcs[] = { 0, };
 static int jz4770_pwm_pwm6_funcs[] = { 0, };
 static int jz4770_pwm_pwm7_funcs[] = { 0, };
+static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_mac_mii_funcs[] = { 0, 0, };
 
 static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
@@ -445,12 +463,18 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
+	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
+	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
+	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
+	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
+	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
@@ -472,6 +496,8 @@ static const struct group_desc jz4770_groups[] = {
 	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
 	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
 	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
+	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
+	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
 };
 
 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -486,9 +512,13 @@ static const char *jz4770_mmc1_groups[] = {
 	"mmc1-1bit-d", "mmc1-4bit-d",
 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 };
+static const char *jz4770_mmc2_groups[] = {
+	"mmc2-1bit-b", "mmc2-4bit-b",
+	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
+};
 static const char *jz4770_nemc_groups[] = {
 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
-	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
+	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 };
 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
@@ -509,6 +539,7 @@ static const char *jz4770_pwm4_groups[] = { "pwm4", };
 static const char *jz4770_pwm5_groups[] = { "pwm5", };
 static const char *jz4770_pwm6_groups[] = { "pwm6", };
 static const char *jz4770_pwm7_groups[] = { "pwm7", };
+static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
 
 static const struct function_desc jz4770_functions[] = {
 	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
@@ -517,6 +548,7 @@ static const struct function_desc jz4770_functions[] = {
 	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
 	{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
 	{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
+	{ "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
 	{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
@@ -537,6 +569,7 @@ static const struct function_desc jz4770_functions[] = {
 	{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
 	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
 	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+	{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
 };
 
 static const struct ingenic_chip_info jz4770_chip_info = {
@@ -584,11 +617,16 @@ static const struct group_desc jz4780_groups[] = {
 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
+	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
+	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
+	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
+	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
 	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
+	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
@@ -623,9 +661,12 @@ static const char *jz4780_mmc0_groups[] = {
 static const char *jz4780_mmc1_groups[] = {
 	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
 };
+static const char *jz4780_mmc2_groups[] = {
+	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
+};
 static const char *jz4780_nemc_groups[] = {
 	"nemc-data", "nemc-cle-ale", "nemc-addr",
-	"nemc-rd-we", "nemc-frd-fwe",
+	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 };
 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
@@ -639,6 +680,7 @@ static const struct function_desc jz4780_functions[] = {
 	{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
 	{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
 	{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
+	{ "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
 	{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
-- 
2.7.4



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_".
  2019-01-28 15:19 ` Ingenic pinctrl fixes Zhou Yanjie
  2019-01-28 15:19   ` [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
  2019-01-28 15:19   ` [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
@ 2019-01-28 15:19   ` Zhou Yanjie
  2019-01-28 18:18     ` Paul Cercueil
  2019-01-30  9:31     ` Linus Walleij
  2 siblings, 2 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-28 15:19 UTC (permalink / raw)
  To: linus.walleij
  Cc: linux-mips, linux-gpio, linux-kernel, paul.burton, paul, syq,
	jiaxun.yang, 772753199, Zhou Yanjie

From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

In the original code, some function names begin with "ingenic_gpio_",
and some with "gpio_ingenic_". For the sake of uniform style,
all of them are changed to the beginning of "ingenic_gpio_".

Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
---
 drivers/pinctrl/pinctrl-ingenic.c | 46 +++++++++++++++++++--------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 6501f35..2b3f7e4 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -715,7 +715,7 @@ static const struct ingenic_chip_info jz4780_chip_info = {
 	.pull_downs = jz4770_pull_downs,
 };
 
-static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
+static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 {
 	unsigned int val;
 
@@ -724,7 +724,7 @@ static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 	return (u32) val;
 }
 
-static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
+static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
 		u8 reg, u8 offset, bool set)
 {
 	if (set)
@@ -738,7 +738,7 @@ static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
 					  u8 offset)
 {
-	unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
+	unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
 
 	return !!(val & BIT(offset));
 }
@@ -747,9 +747,9 @@ static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
 				   u8 offset, int value)
 {
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
 }
 
 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
@@ -767,21 +767,21 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
 
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, true);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, true);
 		break;
 	case IRQ_TYPE_LEVEL_HIGH:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, false);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
 	default:
-		gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-		gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+		ingenic_gpio_set_bit(jzgc, reg1, offset, false);
 		break;
 	}
 }
@@ -791,7 +791,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd)
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-	gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
+	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
 }
 
 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
@@ -799,7 +799,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
 	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-	gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
+	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
 }
 
 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
@@ -809,9 +809,9 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
 	int irq = irqd->hwirq;
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
 
 	ingenic_gpio_irq_unmask(irqd);
 }
@@ -825,9 +825,9 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
 	ingenic_gpio_irq_mask(irqd);
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
 }
 
 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
@@ -850,9 +850,9 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd)
 	}
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
+		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
 	else
-		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
+		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
 }
 
 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -907,9 +907,9 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
 	chained_irq_enter(irq_chip, desc);
 
 	if (jzgc->jzpc->version >= ID_JZ4770)
-		flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
+		flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
 	else
-		flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
+		flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
 
 	for_each_set_bit(i, &flag, 32)
 		generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
-- 
2.7.4



^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.
  2019-01-28 15:19   ` [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
@ 2019-01-28 18:13     ` Paul Cercueil
  2019-01-30  9:30     ` Linus Walleij
  1 sibling, 0 replies; 22+ messages in thread
From: Paul Cercueil @ 2019-01-28 18:13 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linus.walleij, linux-mips, linux-gpio, linux-kernel, paul.burton,
	syq, jiaxun.yang, 772753199, Zhou Yanjie

Hi,

Le lun. 28 janv. 2019 à 12:19, Zhou Yanjie <zhouyanjie@zoho.com> a 
écrit :
> From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
> 
> Add mmc2 for JZ4770 and JZ4780:
> According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
> part of the original code is missing. It is worth noting that JZ4770's
> mmc2 supports 8bit mode while JZ4780's does not, so we added the
> corresponding code for both models.
> 
> Add nemc-wait for JZ4770 and JZ4780:
> Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the
> original code is missing.
> 
> Add mac for JZ4770:
> JZ4770 have a mac. But this part of the original code is missing.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Reviewed-by: Paul Cercueil <paul@crapouillou.net>

Good job!

> ---
>  drivers/pinctrl/pinctrl-ingenic.c | 46 
> +++++++++++++++++++++++++++++++++++++--
>  1 file changed, 44 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
> b/drivers/pinctrl/pinctrl-ingenic.c
> index 710062b..6501f35 100644
> --- a/drivers/pinctrl/pinctrl-ingenic.c
> +++ b/drivers/pinctrl/pinctrl-ingenic.c
> @@ -335,6 +335,11 @@ static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 
> 0x76, 0x77, };
>  static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
>  static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
>  static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
> +static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
> +static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
> +static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
> +static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
> +static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
>  static int jz4770_nemc_8bit_data_pins[] = {
>  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
>  };
> @@ -345,6 +350,7 @@ static int jz4770_nemc_cle_ale_pins[] = { 0x20, 
> 0x21, };
>  static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
>  static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
>  static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
> +static int jz4770_nemc_wait_pins[] = { 0x1b, };
>  static int jz4770_nemc_cs1_pins[] = { 0x15, };
>  static int jz4770_nemc_cs2_pins[] = { 0x16, };
>  static int jz4770_nemc_cs3_pins[] = { 0x17, };
> @@ -375,6 +381,10 @@ static int jz4770_pwm_pwm4_pins[] = { 0x84, };
>  static int jz4770_pwm_pwm5_pins[] = { 0x85, };
>  static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
>  static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
> +static int jz4770_mac_rmii_pins[] = {
> +	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
> +};
> +static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
> 
>  static int jz4770_uart0_data_funcs[] = { 0, 0, };
>  static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
> @@ -394,12 +404,18 @@ static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 
> 0, };
>  static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
>  static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
>  static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
> +static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
> +static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
> +static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
> +static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
> +static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
>  static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 
> };
>  static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 
> 0, };
>  static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
>  static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
>  static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
>  static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
> +static int jz4770_nemc_wait_funcs[] = { 0, };
>  static int jz4770_nemc_cs1_funcs[] = { 0, };
>  static int jz4770_nemc_cs2_funcs[] = { 0, };
>  static int jz4770_nemc_cs3_funcs[] = { 0, };
> @@ -425,6 +441,8 @@ static int jz4770_pwm_pwm4_funcs[] = { 0, };
>  static int jz4770_pwm_pwm5_funcs[] = { 0, };
>  static int jz4770_pwm_pwm6_funcs[] = { 0, };
>  static int jz4770_pwm_pwm7_funcs[] = { 0, };
> +static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
> };
> +static int jz4770_mac_mii_funcs[] = { 0, 0, };
> 
>  static const struct group_desc jz4770_groups[] = {
>  	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
> @@ -445,12 +463,18 @@ static const struct group_desc jz4770_groups[] 
> = {
>  	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
>  	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
>  	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
> +	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
> +	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
> +	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
> +	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
> +	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
>  	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
>  	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
>  	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
>  	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
>  	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
>  	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
> +	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
>  	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
>  	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
>  	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
> @@ -472,6 +496,8 @@ static const struct group_desc jz4770_groups[] = {
>  	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
>  	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
>  	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
> +	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
> +	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
>  };
> 
>  static const char *jz4770_uart0_groups[] = { "uart0-data", 
> "uart0-hwflow", };
> @@ -486,9 +512,13 @@ static const char *jz4770_mmc1_groups[] = {
>  	"mmc1-1bit-d", "mmc1-4bit-d",
>  	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
>  };
> +static const char *jz4770_mmc2_groups[] = {
> +	"mmc2-1bit-b", "mmc2-4bit-b",
> +	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
> +};
>  static const char *jz4770_nemc_groups[] = {
>  	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
> -	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
> +	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
>  };
>  static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
>  static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
> @@ -509,6 +539,7 @@ static const char *jz4770_pwm4_groups[] = { 
> "pwm4", };
>  static const char *jz4770_pwm5_groups[] = { "pwm5", };
>  static const char *jz4770_pwm6_groups[] = { "pwm6", };
>  static const char *jz4770_pwm7_groups[] = { "pwm7", };
> +static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
> 
>  static const struct function_desc jz4770_functions[] = {
>  	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
> @@ -517,6 +548,7 @@ static const struct function_desc 
> jz4770_functions[] = {
>  	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
>  	{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
>  	{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
> +	{ "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
>  	{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
>  	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
>  	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
> @@ -537,6 +569,7 @@ static const struct function_desc 
> jz4770_functions[] = {
>  	{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
>  	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
>  	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
> +	{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
>  };
> 
>  static const struct ingenic_chip_info jz4770_chip_info = {
> @@ -584,11 +617,16 @@ static const struct group_desc jz4780_groups[] 
> = {
>  	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
>  	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
>  	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
> +	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
> +	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
> +	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
> +	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
>  	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
>  	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
>  	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
>  	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
>  	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
> +	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
>  	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
>  	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
>  	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
> @@ -623,9 +661,12 @@ static const char *jz4780_mmc0_groups[] = {
>  static const char *jz4780_mmc1_groups[] = {
>  	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
>  };
> +static const char *jz4780_mmc2_groups[] = {
> +	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
> +};
>  static const char *jz4780_nemc_groups[] = {
>  	"nemc-data", "nemc-cle-ale", "nemc-addr",
> -	"nemc-rd-we", "nemc-frd-fwe",
> +	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
>  };
>  static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
>  static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", 
> "i2c4-data-f", };
> @@ -639,6 +680,7 @@ static const struct function_desc 
> jz4780_functions[] = {
>  	{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
>  	{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
>  	{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
> +	{ "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
>  	{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
>  	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
>  	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
> --
> 2.7.4
> 
> 


^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.
  2019-01-28 15:19   ` [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
@ 2019-01-28 18:17     ` Paul Cercueil
  2019-01-30  9:28     ` Linus Walleij
  1 sibling, 0 replies; 22+ messages in thread
From: Paul Cercueil @ 2019-01-28 18:17 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linus.walleij, linux-mips, linux-gpio, linux-kernel, paul.burton,
	syq, jiaxun.yang, 772753199, Zhou Yanjie

Hi,

Le lun. 28 janv. 2019 à 12:19, Zhou Yanjie <zhouyanjie@zoho.com> a 
écrit :
> From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
> 
> Delete uart4 and i2c3/4 from JZ4770:
> According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
> remove it from the JZ4770 code and add a section corresponding the 
> JZ4780.
> 
> Fix bugs in i2c0/1:
> The pin number was wrong in the original code.
> 
> Fix bugs in uart2:
> JZ4770 and JZ4780 have different uart2 pins. So the original section 
> JZ4770
> has been modified and the corresponding section of JZ4780 has been 
> added.
> 
> Fix bugs in mmc0:
> JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. 
> So the
> original section JZ4770 has been modified and the corresponding 
> section of
> JZ4780 has been added.
> 
> Fix bugs in mmc1:
> JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original
> section JZ4770 has been modified and the corresponding section of
> JZ4780 has been added.
> 
> Fix bugs in nemc:
> JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original 
> section
> JZ4770 has been modified and the corresponding section of JZ4780 has 
> been
> added. And add missing cs2~5 groups for JZ4770 and JZ4780.
> 
> Fix bugs in cim:
> JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original
> section JZ4770 has been modified and the corresponding section of
> JZ4780 has been added.
> 
> Fix bugs in lcd:
> Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit.
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Reviewed-by: Paul Cercueil <paul@crapouillou.net>

> ---
>  drivers/pinctrl/pinctrl-ingenic.c | 249 
> +++++++++++++++++++++++++++++---------
>  1 file changed, 191 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
> b/drivers/pinctrl/pinctrl-ingenic.c
> index db6b48e..710062b 100644
> --- a/drivers/pinctrl/pinctrl-ingenic.c
> +++ b/drivers/pinctrl/pinctrl-ingenic.c
> @@ -321,23 +321,26 @@ static int jz4770_uart0_data_pins[] = { 0xa0, 
> 0xa3, };
>  static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
>  static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
>  static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
> -static int jz4770_uart2_data_pins[] = { 0x66, 0x67, };
> -static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, };
> +static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
> +static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
>  static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
>  static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
> -static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, };
> -static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 
> 0x18, };
> -static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
>  static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
> -static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
> +static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
>  static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
> -static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
> +static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
> +static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
>  static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
> -static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
> +static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
>  static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
> -static int jz4770_nemc_data_pins[] = {
> +static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
> +static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
> +static int jz4770_nemc_8bit_data_pins[] = {
>  	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
>  };
> +static int jz4770_nemc_16bit_data_pins[] = {
> +	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
> +};
>  static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
>  static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
>  static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
> @@ -348,20 +351,21 @@ static int jz4770_nemc_cs3_pins[] = { 0x17, };
>  static int jz4770_nemc_cs4_pins[] = { 0x18, };
>  static int jz4770_nemc_cs5_pins[] = { 0x19, };
>  static int jz4770_nemc_cs6_pins[] = { 0x1a, };
> -static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, };
> -static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, };
> +static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
> +static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
>  static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
> -static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, };
> -static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, };
> -static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, };
> -static int jz4770_cim_pins[] = {
> -	0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 
> 0x31,
> +static int jz4770_cim_8bit_pins[] = {
> +	0x26, 0x27, 0x28, 0x29,
> +	0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
> +};
> +static int jz4770_cim_12bit_pins[] = {
> +	0x32, 0x33, 0xb0, 0xb1,
>  };
> -static int jz4770_lcd_32bit_pins[] = {
> +static int jz4770_lcd_24bit_pins[] = {
>  	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
>  	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
>  	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
> -	0x58, 0x59, 0x51,
> +	0x58, 0x59, 0x5a, 0x5b,
>  };
>  static int jz4770_pwm_pwm0_pins[] = { 0x80, };
>  static int jz4770_pwm_pwm1_pins[] = { 0x81, };
> @@ -376,21 +380,22 @@ static int jz4770_uart0_data_funcs[] = { 0, 0, 
> };
>  static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
>  static int jz4770_uart1_data_funcs[] = { 0, 0, };
>  static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
> -static int jz4770_uart2_data_funcs[] = { 1, 1, };
> -static int jz4770_uart2_hwflow_funcs[] = { 1, 1, };
> +static int jz4770_uart2_data_funcs[] = { 0, 0, };
> +static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
>  static int jz4770_uart3_data_funcs[] = { 0, 1, };
>  static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
> -static int jz4770_uart4_data_funcs[] = { 2, 2, };
> -static int jz4770_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
> -static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
>  static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
> -static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
> +static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
>  static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
> -static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
> +static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
> +static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
>  static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
> -static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
> +static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
>  static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
> -static int jz4770_nemc_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
> +static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
> +static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
> +static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 
> };
> +static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 
> 0, };
>  static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
>  static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
>  static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
> @@ -404,14 +409,13 @@ static int jz4770_nemc_cs6_funcs[] = { 0, };
>  static int jz4770_i2c0_funcs[] = { 0, 0, };
>  static int jz4770_i2c1_funcs[] = { 0, 0, };
>  static int jz4770_i2c2_funcs[] = { 2, 2, };
> -static int jz4770_i2c3_funcs[] = { 1, 1, };
> -static int jz4770_i2c4_e_funcs[] = { 1, 1, };
> -static int jz4770_i2c4_f_funcs[] = { 1, 1, };
> -static int jz4770_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
> 0, };
> -static int jz4770_lcd_32bit_funcs[] = {
> +static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
> 0, 0, };
> +static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
> +static int jz4770_lcd_24bit_funcs[] = {
> +	0, 0, 0, 0, 0, 0, 0, 0,
>  	0, 0, 0, 0, 0, 0, 0, 0,
>  	0, 0, 0, 0, 0, 0, 0, 0,
> -	0, 0, 0,
> +	0, 0, 0, 0,
>  };
>  static int jz4770_pwm_pwm0_funcs[] = { 0, };
>  static int jz4770_pwm_pwm1_funcs[] = { 0, };
> @@ -431,17 +435,18 @@ static const struct group_desc jz4770_groups[] 
> = {
>  	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
>  	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
>  	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
> -	INGENIC_PIN_GROUP("uart4-data", jz4770_uart4_data),
> -	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4770_mmc0_8bit_a),
> -	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
>  	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
> -	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
> +	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
>  	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
> -	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
> +	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
> +	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
>  	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
> -	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
> +	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
>  	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
> -	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_data),
> +	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
> +	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
> +	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
> +	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
>  	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
>  	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
>  	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
> @@ -455,11 +460,9 @@ static const struct group_desc jz4770_groups[] = 
> {
>  	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
>  	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
>  	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
> -	INGENIC_PIN_GROUP("i2c3-data", jz4770_i2c3),
> -	INGENIC_PIN_GROUP("i2c4-data-e", jz4770_i2c4_e),
> -	INGENIC_PIN_GROUP("i2c4-data-f", jz4770_i2c4_f),
> -	INGENIC_PIN_GROUP("cim-data", jz4770_cim),
> -	INGENIC_PIN_GROUP("lcd-32bit", jz4770_lcd_32bit),
> +	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
> +	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
> +	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
>  	{ "lcd-no-pins", },
>  	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
>  	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
> @@ -475,26 +478,29 @@ static const char *jz4770_uart0_groups[] = { 
> "uart0-data", "uart0-hwflow", };
>  static const char *jz4770_uart1_groups[] = { "uart1-data", 
> "uart1-hwflow", };
>  static const char *jz4770_uart2_groups[] = { "uart2-data", 
> "uart2-hwflow", };
>  static const char *jz4770_uart3_groups[] = { "uart3-data", 
> "uart3-hwflow", };
> -static const char *jz4770_uart4_groups[] = { "uart4-data", };
>  static const char *jz4770_mmc0_groups[] = {
> -	"mmc0-8bit-a", "mmc0-4bit-a", "mmc0-1bit-a",
> -	"mmc0-1bit-e", "mmc0-4bit-e",
> +	"mmc0-1bit-a", "mmc0-4bit-a",
> +	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
>  };
>  static const char *jz4770_mmc1_groups[] = {
> -	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
> +	"mmc1-1bit-d", "mmc1-4bit-d",
> +	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
>  };
>  static const char *jz4770_nemc_groups[] = {
> -	"nemc-data", "nemc-cle-ale", "nemc-addr", "nemc-rd-we", 
> "nemc-frd-fwe",
> +	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
> +	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe",
>  };
>  static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
> +static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
> +static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
> +static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
> +static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
>  static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
>  static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
>  static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
>  static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
> -static const char *jz4770_i2c3_groups[] = { "i2c3-data", };
> -static const char *jz4770_i2c4_groups[] = { "i2c4-data-e", 
> "i2c4-data-f", };
> -static const char *jz4770_cim_groups[] = { "cim-data", };
> -static const char *jz4770_lcd_groups[] = { "lcd-32bit", 
> "lcd-no-pins", };
> +static const char *jz4770_cim_groups[] = { "cim-data-8bit", 
> "cim-data-12bit", };
> +static const char *jz4770_lcd_groups[] = { "lcd-24bit", 
> "lcd-no-pins", };
>  static const char *jz4770_pwm0_groups[] = { "pwm0", };
>  static const char *jz4770_pwm1_groups[] = { "pwm1", };
>  static const char *jz4770_pwm2_groups[] = { "pwm2", };
> @@ -509,17 +515,18 @@ static const struct function_desc 
> jz4770_functions[] = {
>  	{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
>  	{ "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
>  	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
> -	{ "uart4", jz4770_uart4_groups, ARRAY_SIZE(jz4770_uart4_groups), },
>  	{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
>  	{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
>  	{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
>  	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
> +	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
> +	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
> +	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
> +	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
>  	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
>  	{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
>  	{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
>  	{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
> -	{ "i2c3", jz4770_i2c3_groups, ARRAY_SIZE(jz4770_i2c3_groups), },
> -	{ "i2c4", jz4770_i2c4_groups, ARRAY_SIZE(jz4770_i2c4_groups), },
>  	{ "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
>  	{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
>  	{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
> @@ -542,6 +549,130 @@ static const struct ingenic_chip_info 
> jz4770_chip_info = {
>  	.pull_downs = jz4770_pull_downs,
>  };
> 
> +static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
> +static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
> +static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
> +static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 
> 0x18, };
> +static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
> +static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
> +static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
> +
> +static int jz4780_uart2_data_funcs[] = { 1, 1, };
> +static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
> +static int jz4780_uart4_data_funcs[] = { 2, 2, };
> +static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
> +static int jz4780_i2c3_funcs[] = { 1, 1, };
> +static int jz4780_i2c4_e_funcs[] = { 1, 1, };
> +static int jz4780_i2c4_f_funcs[] = { 1, 1, };
> +
> +static const struct group_desc jz4780_groups[] = {
> +	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
> +	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
> +	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
> +	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
> +	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
> +	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
> +	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
> +	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
> +	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
> +	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
> +	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
> +	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
> +	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
> +	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
> +	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
> +	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
> +	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
> +	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
> +	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
> +	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
> +	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
> +	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
> +	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
> +	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
> +	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
> +	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
> +	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
> +	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
> +	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
> +	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
> +	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
> +	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
> +	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
> +	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
> +	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
> +	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
> +	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
> +	{ "lcd-no-pins", },
> +	INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
> +	INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
> +	INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
> +	INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
> +	INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
> +	INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
> +	INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
> +	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
> +};
> +
> +static const char *jz4780_uart2_groups[] = { "uart2-data", 
> "uart2-hwflow", };
> +static const char *jz4780_uart4_groups[] = { "uart4-data", };
> +static const char *jz4780_mmc0_groups[] = {
> +	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
> +	"mmc0-1bit-e", "mmc0-4bit-e",
> +};
> +static const char *jz4780_mmc1_groups[] = {
> +	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
> +};
> +static const char *jz4780_nemc_groups[] = {
> +	"nemc-data", "nemc-cle-ale", "nemc-addr",
> +	"nemc-rd-we", "nemc-frd-fwe",
> +};
> +static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
> +static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", 
> "i2c4-data-f", };
> +static const char *jz4780_cim_groups[] = { "cim-data", };
> +
> +static const struct function_desc jz4780_functions[] = {
> +	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
> +	{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
> +	{ "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
> +	{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
> +	{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
> +	{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
> +	{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
> +	{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
> +	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
> +	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
> +	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
> +	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
> +	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
> +	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
> +	{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
> +	{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
> +	{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
> +	{ "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
> +	{ "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
> +	{ "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
> +	{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
> +	{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
> +	{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
> +	{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
> +	{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
> +	{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
> +	{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
> +	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
> +	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
> +};
> +
> +static const struct ingenic_chip_info jz4780_chip_info = {
> +	.num_chips = 6,
> +	.groups = jz4780_groups,
> +	.num_groups = ARRAY_SIZE(jz4780_groups),
> +	.functions = jz4780_functions,
> +	.num_functions = ARRAY_SIZE(jz4780_functions),
> +	.pull_ups = jz4770_pull_ups,
> +	.pull_downs = jz4770_pull_downs,
> +};
> +
>  static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 
> reg)
>  {
>  	unsigned int val;
> @@ -1185,7 +1316,9 @@ static int __init ingenic_pinctrl_probe(struct 
> platform_device *pdev)
>  	else
>  		jzpc->version = (enum jz_version)id->driver_data;
> 
> -	if (jzpc->version >= ID_JZ4770)
> +	if (jzpc->version >= ID_JZ4780)
> +		chip_info = &jz4780_chip_info;
> +	else if (jzpc->version >= ID_JZ4770)
>  		chip_info = &jz4770_chip_info;
>  	else if (jzpc->version >= ID_JZ4725B)
>  		chip_info = &jz4725b_chip_info;
> --
> 2.7.4
> 
> 


^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_".
  2019-01-28 15:19   ` [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
@ 2019-01-28 18:18     ` Paul Cercueil
  2019-01-30  9:31     ` Linus Walleij
  1 sibling, 0 replies; 22+ messages in thread
From: Paul Cercueil @ 2019-01-28 18:18 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linus.walleij, linux-mips, linux-gpio, linux-kernel, paul.burton,
	syq, jiaxun.yang, 772753199, Zhou Yanjie



Le lun. 28 janv. 2019 à 12:19, Zhou Yanjie <zhouyanjie@zoho.com> a 
écrit :
> From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
> 
> In the original code, some function names begin with "ingenic_gpio_",
> and some with "gpio_ingenic_". For the sake of uniform style,
> all of them are changed to the beginning of "ingenic_gpio_".
> 
> Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Reviewed-by: Paul Cercueil <paul@crapouillou.net>

> ---
>  drivers/pinctrl/pinctrl-ingenic.c | 46 
> +++++++++++++++++++--------------------
>  1 file changed, 23 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
> b/drivers/pinctrl/pinctrl-ingenic.c
> index 6501f35..2b3f7e4 100644
> --- a/drivers/pinctrl/pinctrl-ingenic.c
> +++ b/drivers/pinctrl/pinctrl-ingenic.c
> @@ -715,7 +715,7 @@ static const struct ingenic_chip_info 
> jz4780_chip_info = {
>  	.pull_downs = jz4770_pull_downs,
>  };
> 
> -static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 
> reg)
> +static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 
> reg)
>  {
>  	unsigned int val;
> 
> @@ -724,7 +724,7 @@ static u32 gpio_ingenic_read_reg(struct 
> ingenic_gpio_chip *jzgc, u8 reg)
>  	return (u32) val;
>  }
> 
> -static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
> +static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
>  		u8 reg, u8 offset, bool set)
>  {
>  	if (set)
> @@ -738,7 +738,7 @@ static void gpio_ingenic_set_bit(struct 
> ingenic_gpio_chip *jzgc,
>  static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip 
> *jzgc,
>  					  u8 offset)
>  {
> -	unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
> +	unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
> 
>  	return !!(val & BIT(offset));
>  }
> @@ -747,9 +747,9 @@ static void ingenic_gpio_set_value(struct 
> ingenic_gpio_chip *jzgc,
>  				   u8 offset, int value)
>  {
>  	if (jzgc->jzpc->version >= ID_JZ4770)
> -		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
> +		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
>  	else
> -		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
> +		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
>  }
> 
>  static void irq_set_type(struct ingenic_gpio_chip *jzgc,
> @@ -767,21 +767,21 @@ static void irq_set_type(struct 
> ingenic_gpio_chip *jzgc,
> 
>  	switch (type) {
>  	case IRQ_TYPE_EDGE_RISING:
> -		gpio_ingenic_set_bit(jzgc, reg2, offset, true);
> -		gpio_ingenic_set_bit(jzgc, reg1, offset, true);
> +		ingenic_gpio_set_bit(jzgc, reg2, offset, true);
> +		ingenic_gpio_set_bit(jzgc, reg1, offset, true);
>  		break;
>  	case IRQ_TYPE_EDGE_FALLING:
> -		gpio_ingenic_set_bit(jzgc, reg2, offset, false);
> -		gpio_ingenic_set_bit(jzgc, reg1, offset, true);
> +		ingenic_gpio_set_bit(jzgc, reg2, offset, false);
> +		ingenic_gpio_set_bit(jzgc, reg1, offset, true);
>  		break;
>  	case IRQ_TYPE_LEVEL_HIGH:
> -		gpio_ingenic_set_bit(jzgc, reg2, offset, true);
> -		gpio_ingenic_set_bit(jzgc, reg1, offset, false);
> +		ingenic_gpio_set_bit(jzgc, reg2, offset, true);
> +		ingenic_gpio_set_bit(jzgc, reg1, offset, false);
>  		break;
>  	case IRQ_TYPE_LEVEL_LOW:
>  	default:
> -		gpio_ingenic_set_bit(jzgc, reg2, offset, false);
> -		gpio_ingenic_set_bit(jzgc, reg1, offset, false);
> +		ingenic_gpio_set_bit(jzgc, reg2, offset, false);
> +		ingenic_gpio_set_bit(jzgc, reg1, offset, false);
>  		break;
>  	}
>  }
> @@ -791,7 +791,7 @@ static void ingenic_gpio_irq_mask(struct irq_data 
> *irqd)
>  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
>  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
> 
> -	gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
> +	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
>  }
> 
>  static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
> @@ -799,7 +799,7 @@ static void ingenic_gpio_irq_unmask(struct 
> irq_data *irqd)
>  	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
>  	struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
> 
> -	gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
> +	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
>  }
> 
>  static void ingenic_gpio_irq_enable(struct irq_data *irqd)
> @@ -809,9 +809,9 @@ static void ingenic_gpio_irq_enable(struct 
> irq_data *irqd)
>  	int irq = irqd->hwirq;
> 
>  	if (jzgc->jzpc->version >= ID_JZ4770)
> -		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
> +		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
>  	else
> -		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
> +		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
> 
>  	ingenic_gpio_irq_unmask(irqd);
>  }
> @@ -825,9 +825,9 @@ static void ingenic_gpio_irq_disable(struct 
> irq_data *irqd)
>  	ingenic_gpio_irq_mask(irqd);
> 
>  	if (jzgc->jzpc->version >= ID_JZ4770)
> -		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
> +		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
>  	else
> -		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
> +		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
>  }
> 
>  static void ingenic_gpio_irq_ack(struct irq_data *irqd)
> @@ -850,9 +850,9 @@ static void ingenic_gpio_irq_ack(struct irq_data 
> *irqd)
>  	}
> 
>  	if (jzgc->jzpc->version >= ID_JZ4770)
> -		gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
> +		ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
>  	else
> -		gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
> +		ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
>  }
> 
>  static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned 
> int type)
> @@ -907,9 +907,9 @@ static void ingenic_gpio_irq_handler(struct 
> irq_desc *desc)
>  	chained_irq_enter(irq_chip, desc);
> 
>  	if (jzgc->jzpc->version >= ID_JZ4770)
> -		flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG);
> +		flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
>  	else
> -		flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG);
> +		flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
> 
>  	for_each_set_bit(i, &flag, 32)
>  		generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
> --
> 2.7.4
> 
> 


^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration.
  2019-01-25 17:59   ` Paul Cercueil
  2019-01-26  8:23     ` Zhou Yanjie
@ 2019-01-28 19:22     ` Joe Perches
  2019-01-29  4:06       ` Zhou Yanjie
  1 sibling, 1 reply; 22+ messages in thread
From: Joe Perches @ 2019-01-28 19:22 UTC (permalink / raw)
  To: Paul Cercueil, Zhou Yanjie
  Cc: linus.walleij, linux-mips, linux-gpio, linux-kernel, paul.burton,
	syq, jiaxun.yang, 772753199

On Fri, 2019-01-25 at 14:59 -0300, Paul Cercueil wrote:
> On Fri, Jan 25, 2019 at 6:59 AM, Zhou Yanjie <zhouyanjie@zoho.com> 
> wrote:
> > Warning is reported when checkpatch indicates that
> > "static const char * array" should be changed to
> > "static const char * const".
[]
> > diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
[]
> > @@ -172,23 +172,25 @@ static const struct group_desc jz4740_groups[] 
[]
> > +static const char * const jz4740_mmc_groups[] = { "mmc-1bit", 
> > "mmc-4bit", };
> >  static const struct function_desc jz4740_functions[] = {
> >  	{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
> 
> With this patch applied I get this:
> 
> drivers/pinctrl/pinctrl-ingenic.c:196:11: attention : initialization 
> discards
> ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
>   { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
>            ^~~~~~~~~~~~~~~~~

You could change group_names to const char * const group_names
in pinmux.h

---
 drivers/pinctrl/pinmux.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 3319535c76cb..2b903774ba5c 100644
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -122,7 +122,7 @@ static inline void pinmux_init_device_debugfs(struct dentry *devroot,
  */
 struct function_desc {
 	const char *name;
-	const char **group_names;
+	const char * const *group_names;
 	int num_group_names;
 	void *data;
 };



^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration.
  2019-01-28 19:22     ` Joe Perches
@ 2019-01-29  4:06       ` Zhou Yanjie
  0 siblings, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-01-29  4:06 UTC (permalink / raw)
  To: Joe Perches, Paul Cercueil
  Cc: linus.walleij, linux-mips, linux-gpio, linux-kernel, paul.burton,
	syq, jiaxun.yang, 772753199

I would prefer to keep it. There are many other drivers that also use 
this header file.

On 2019年01月29日 03:22, Joe Perches wrote:
> On Fri, 2019-01-25 at 14:59 -0300, Paul Cercueil wrote:
>> On Fri, Jan 25, 2019 at 6:59 AM, Zhou Yanjie <zhouyanjie@zoho.com>
>> wrote:
>>> Warning is reported when checkpatch indicates that
>>> "static const char * array" should be changed to
>>> "static const char * const".
> []
>>> diff --git a/drivers/pinctrl/pinctrl-ingenic.c
> []
>>> @@ -172,23 +172,25 @@ static const struct group_desc jz4740_groups[]
> []
>>> +static const char * const jz4740_mmc_groups[] = { "mmc-1bit",
>>> "mmc-4bit", };
>>>   static const struct function_desc jz4740_functions[] = {
>>>   	{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
>> With this patch applied I get this:
>>
>> drivers/pinctrl/pinctrl-ingenic.c:196:11: attention : initialization
>> discards
>> ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
>>    { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
>>             ^~~~~~~~~~~~~~~~~
> You could change group_names to const char * const group_names
> in pinmux.h
>
> ---
>   drivers/pinctrl/pinmux.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
> index 3319535c76cb..2b903774ba5c 100644
> --- a/drivers/pinctrl/pinmux.h
> +++ b/drivers/pinctrl/pinmux.h
> @@ -122,7 +122,7 @@ static inline void pinmux_init_device_debugfs(struct dentry *devroot,
>    */
>   struct function_desc {
>   	const char *name;
> -	const char **group_names;
> +	const char * const *group_names;
>   	int num_group_names;
>   	void *data;
>   };
>
>




^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.
  2019-01-28 15:19   ` [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
  2019-01-28 18:17     ` Paul Cercueil
@ 2019-01-30  9:28     ` Linus Walleij
  1 sibling, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2019-01-30  9:28 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, open list:GPIO SUBSYSTEM, linux-kernel, Paul Burton,
	Paul Cercueil, syq, Jiaxun Yang, 772753199, Zhou Yanjie

On Mon, Jan 28, 2019 at 4:28 PM Zhou Yanjie <zhouyanjie@zoho.com> wrote:

> From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
>
> Delete uart4 and i2c3/4 from JZ4770:
> According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
> remove it from the JZ4770 code and add a section corresponding the JZ4780.
>
> Fix bugs in i2c0/1:
> The pin number was wrong in the original code.
>
> Fix bugs in uart2:
> JZ4770 and JZ4780 have different uart2 pins. So the original section JZ4770
> has been modified and the corresponding section of JZ4780 has been added.
>
> Fix bugs in mmc0:
> JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. So the
> original section JZ4770 has been modified and the corresponding section of
> JZ4780 has been added.
>
> Fix bugs in mmc1:
> JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original
> section JZ4770 has been modified and the corresponding section of
> JZ4780 has been added.
>
> Fix bugs in nemc:
> JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original section
> JZ4770 has been modified and the corresponding section of JZ4780 has been
> added. And add missing cs2~5 groups for JZ4770 and JZ4780.
>
> Fix bugs in cim:
> JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original
> section JZ4770 has been modified and the corresponding section of
> JZ4780 has been added.
>
> Fix bugs in lcd:
> Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Patch applied for v5.1 with Paul's review tag.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.
  2019-01-28 15:19   ` [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
  2019-01-28 18:13     ` Paul Cercueil
@ 2019-01-30  9:30     ` Linus Walleij
  1 sibling, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2019-01-30  9:30 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, open list:GPIO SUBSYSTEM, linux-kernel, Paul Burton,
	Paul Cercueil, syq, Jiaxun Yang, 772753199, Zhou Yanjie

On Mon, Jan 28, 2019 at 4:28 PM Zhou Yanjie <zhouyanjie@zoho.com> wrote:

> From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
>
> Add mmc2 for JZ4770 and JZ4780:
> According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
> part of the original code is missing. It is worth noting that JZ4770's
> mmc2 supports 8bit mode while JZ4780's does not, so we added the
> corresponding code for both models.
>
> Add nemc-wait for JZ4770 and JZ4780:
> Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the
> original code is missing.
>
> Add mac for JZ4770:
> JZ4770 have a mac. But this part of the original code is missing.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Patch applied with Paul's ACK!

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_".
  2019-01-28 15:19   ` [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
  2019-01-28 18:18     ` Paul Cercueil
@ 2019-01-30  9:31     ` Linus Walleij
  1 sibling, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2019-01-30  9:31 UTC (permalink / raw)
  To: Zhou Yanjie
  Cc: linux-mips, open list:GPIO SUBSYSTEM, linux-kernel, Paul Burton,
	Paul Cercueil, syq, Jiaxun Yang, 772753199, Zhou Yanjie

On Mon, Jan 28, 2019 at 4:29 PM Zhou Yanjie <zhouyanjie@zoho.com> wrote:

> From: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>
>
> In the original code, some function names begin with "ingenic_gpio_",
> and some with "gpio_ingenic_". For the sake of uniform style,
> all of them are changed to the beginning of "ingenic_gpio_".
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@cduestc.edu.cn>

Patch applied with Paul's ACK!

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, back to index

Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-25  9:59 Ingenic pinctrl fixes Zhou Yanjie
2019-01-25  9:59 ` [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
2019-01-28 13:59   ` Linus Walleij
2019-01-28 14:42     ` Zhou Yanjie
2019-01-28 14:47       ` Linus Walleij
2019-01-25  9:59 ` [PATCH RESEND 2/4] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
2019-01-25  9:59 ` [PATCH RESEND 3/4] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
2019-01-25  9:59 ` [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration Zhou Yanjie
2019-01-25 17:59   ` Paul Cercueil
2019-01-26  8:23     ` Zhou Yanjie
2019-01-28 19:22     ` Joe Perches
2019-01-29  4:06       ` Zhou Yanjie
2019-01-28 15:19 ` Ingenic pinctrl fixes Zhou Yanjie
2019-01-28 15:19   ` [PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780 Zhou Yanjie
2019-01-28 18:17     ` Paul Cercueil
2019-01-30  9:28     ` Linus Walleij
2019-01-28 15:19   ` [PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for " Zhou Yanjie
2019-01-28 18:13     ` Paul Cercueil
2019-01-30  9:30     ` Linus Walleij
2019-01-28 15:19   ` [PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_" Zhou Yanjie
2019-01-28 18:18     ` Paul Cercueil
2019-01-30  9:31     ` Linus Walleij

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