From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3935C3A59B for ; Sat, 17 Aug 2019 14:42:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A294521744 for ; Sat, 17 Aug 2019 14:42:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UWWveDza" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726083AbfHQOmY (ORCPT ); Sat, 17 Aug 2019 10:42:24 -0400 Received: from mail-ot1-f66.google.com ([209.85.210.66]:33050 "EHLO mail-ot1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725832AbfHQOmY (ORCPT ); Sat, 17 Aug 2019 10:42:24 -0400 Received: by mail-ot1-f66.google.com with SMTP id q20so11445941otl.0; Sat, 17 Aug 2019 07:42:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=u+ouuMQrNVti/jSM5pYCBsXYcjd9f+fOqg85jip3rp8=; b=UWWveDzaXrnRWzm77yDCOLyoGFGeMfwlcrcoDAlg+n2BRt2WEWB+dpBiXK97kiEVRW YLslFXHdVfC/GFkbxBh6Gdu+SWw8331QjQC4zEte152sB0ESTXRTCOUbwt/2NLDYtOKx 8x4YttqP2cffWMMb59Y5HOAWsDO97/1519Du2PTbYAKeCg14TS/QiD6i9PDXlLQWNvXR 6kslMkAzXMm9HtWfEnB4f0gVx6gPQn57wPLjuujlARLCoOugYV8BGr1cOT43lj9FNhae QlaM/ig6tXqy2Ch72M9GC//cNQXpQ6crg3hfg3Q0rHRMqQ/FIk0B3+y5YmIQCpkT+Wi1 GWWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=u+ouuMQrNVti/jSM5pYCBsXYcjd9f+fOqg85jip3rp8=; b=VkoUw6yaygih1gnIuD+w142Wc52KdPj/pYd/8kXL0vILO6afv1lyvmql/PiTjw2+Ux t1QVgqlghUUvc7Yvpuo4AYCChXA5eCKTXtewnkWAXg6/udfesnXlwqbQWjtIY6x75zq+ PRBa9KNY9OJJPPWjeyMIMbpHnW8wB/wxuclDeZnioEOTMYRgqEaP2Ad0bUfLXPoSgy8S aKn0w+xDEPY7rB1qRFqDcuVLHvb7iHcXsjHdj5eErVHtTBMYZWKbSRpYjmg3XD94aVUz YJDUBOE4m5JLiNsdh50xyUXqIdQvaYzg2yeaILt2+OxamPSbWFp5+/T/5B10nVBOqA63 S3GQ== X-Gm-Message-State: APjAAAWzOO9QVJNl8CQ52xPKSENAPVDiXouy2xQxdo8Hu7FhzMyR3WQ9 tmlXNksdDi8PjXrbwDjIM3JvTtZZFK1KKODJDRg= X-Google-Smtp-Source: APXvYqz5ceM2JCDDDSIcgUhj8lMv5v0FOmMnXg2IeO6sSggcznPDuJampGWaCUwiZ5tB3C/ohH295tN+dd8XvA8ef8o= X-Received: by 2002:a05:6830:1592:: with SMTP id i18mr5384197otr.86.1566052943046; Sat, 17 Aug 2019 07:42:23 -0700 (PDT) MIME-Version: 1.0 References: <20190724022310.28010-1-gch981213@gmail.com> <20190724022310.28010-5-gch981213@gmail.com> <20190813155143.GA19830@bogus> In-Reply-To: <20190813155143.GA19830@bogus> From: Chuanhong Guo Date: Sat, 17 Aug 2019 22:42:12 +0800 Message-ID: Subject: Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation To: Rob Herring Cc: "open list:COMMON CLK FRAMEWORK" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , "open list:MIPS" , "open list:STAGING SUBSYSTEM" , Michael Turquette , Stephen Boyd , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , John Crispin , Greg Kroah-Hartman , Weijie Gao , NeilBrown Content-Type: text/plain; charset="UTF-8" Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Hi! On Tue, Aug 13, 2019 at 11:51 PM Rob Herring wrote: > [...] > > +Example: > > + pll { > > + compatible = "mediatek,mt7621-pll"; > > You didn't answer Stephen's question on v1. I thought he was asking why there's a syscon in compatible string. I noticed that the syscon in my previous patch is a copy-paste error from elsewhere and dropped it. > > Based on this binding, there is no way to control/program the PLL. Is > this part of some IP block? The entire section is called "system control" in datasheet and is occupied in arch/mips/ralink/mt7621.c [0] Two clocks provided here is determined by reading some read-only registers in this part. There's another register in this section providing clock gates for every peripherals, but MTK doesn't provide a clock plan in their datasheet. I can't determine corresponding clock frequencies for every peripherals, thus unable to write a working clock driver. > > > + > > + #clock-cells = <1>; > > + clock-output-names = "cpu", "bus"; > > + }; > > -- > > 2.21.0 > > Regards, Chuanhong Guo [0] https://elixir.bootlin.com/linux/latest/source/arch/mips/ralink/mt7621.c#L156