From: Chuanhong Guo <gch981213@gmail.com>
To: Oleksij Rempel <fishor@gmx.net>
Cc: Rob Herring <robh@kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
"open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paul.burton@mips.com>,
James Hogan <jhogan@kernel.org>, John Crispin <john@phrozen.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Weijie Gao <hackpascal@gmail.com>, NeilBrown <neil@brown.name>
Subject: Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation
Date: Sun, 18 Aug 2019 00:22:49 +0800 [thread overview]
Message-ID: <CAJsYDVLq1-U_AngA4=YKHS_L=zurhLse9XwQ0Rzup9BdXfri-w@mail.gmail.com> (raw)
In-Reply-To: <2d48f4a4-7d30-547b-21ee-6aadabe7d7c3@gmx.net>
Hi!
On Sat, Aug 17, 2019 at 11:40 PM Oleksij Rempel <fishor@gmx.net> wrote:
> In provided link [0] the ralink_clk_init function is reading SYSC_REG_CPLL_CLKCFG0 R/W register.
> This register is used to determine clock source, clock freq and CPU or bus clocks.
This register should only be changed by bootloader, not kernel. So
it's read-only in kernel's perspective.
> SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks.
> Jist wild assumption. All peripheral devices are suing bus clock.
This assumption is incorrect. When this patchset is applied in
OpenWrt, I asked the author why there's still a fixed clock in
mt7621.dtsi, He told me that there's another clock for those unchanged
peripherals and he doesn't have time to write a clock provider for it.
I don't know how many undocumented clocks are there since this piece
of info is missing in datasheet.
>
> IMO - this information is enough to create full blown drivers/clk/mediatek/clk-mt7621.c
And this information isn't enough because the assumption above is incorrect :P
Regards,
Chuanhong Guo
next prev parent reply other threads:[~2019-08-17 16:23 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-24 2:23 [PATCH v2 0/6] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 1/6] dt-bindings: clock: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 2/6] MIPS: ralink: drop ralink_clk_init for mt7621 Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 3/6] MIPS: ralink: add clock device providing cpu/bus clock " Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
2019-07-29 17:33 ` Paul Burton
2019-08-13 15:51 ` Rob Herring
2019-08-17 14:42 ` Chuanhong Guo
2019-08-17 15:39 ` Oleksij Rempel
2019-08-17 16:22 ` Chuanhong Guo [this message]
2019-08-17 18:05 ` Oleksij Rempel
2019-08-18 2:29 ` Chuanhong Guo
2019-08-18 6:10 ` Oleksij Rempel
2019-08-18 7:19 ` Chuanhong Guo
2019-08-18 7:59 ` Oleksij Rempel
2019-08-18 8:26 ` Chuanhong Guo
2019-08-18 8:44 ` Chuanhong Guo
2019-08-18 9:51 ` Oleksij Rempel
2019-08-18 10:07 ` Chuanhong Guo
2019-08-17 15:40 ` Oleksij Rempel
2019-07-24 2:23 ` [PATCH v2 5/6] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 6/6] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
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