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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: mR3sAoEJ4txoCcNkqmVbZhdFdRx54ZuYfFCcd02s88gn9J4xo6+4KYiAWf3OdtgaOXs2hrNnFDOPEFisyU3B9rGu4PtRMPlb/tGgOJLwu3cmhmI+kg1haWoMtrVjCpzBxxr9jJNJe3CVZeSFJMf1ZAdqWcGXSZvEw2kh6NT4G9lJRNgSINNbcY7kRpZBtjs76dZF2mL4nRpyPHVyo9WglKPKt/4+8f7VJUbxXDQ4yuZgMkDkuBdVXIuJFMX1+r3fch/GxEibvWyG8K8/S384ocGPziTL/vorv0MLpSMHHlywsXq0rebjgbt15YtvVH+I spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 303da6c8-85d5-4224-26ba-08d674e8af84 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jan 2019 21:40:05.1505 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1760 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Hello, Hauke Mehrtens wrote: > This makes SMP on the vrx200 work again, by removing all the MIPS CPU > interrupt specific code and making it fully use the generic MIPS CPU > interrupt controller. >=20 > The mti,cpu-interrupt-controller from irq-mips-cpu.c now handles the CPU > interrupts and also the IPI interrupts which are used to communication > between the CPUs in a SMP system. The generic interrupt code was > already used before but the interrupt vectors were overwritten again > when we called set_vi_handler() in the lantiq interrupt driver and we > also provided our own plat_irq_dispatch() function which overwrote the > weak generic implementation. Now the code uses the generic handler for > the MIPS CPU interrupts including the IPI interrupts and registers a > handler for the CPU interrupts which are handled by the lantiq ICU with > irq_set_chained_handler() which was already called before. >=20 > Calling the set_c0_status() function is also not needed any more because > the generic MIPS CPU interrupt already activates the needed bits. >=20 > Fixes 1eed40043579 ("MIPS: smp-mt: Use CPU interrupt controller IPI IRQ d= omain support") > Cc: stable@kernel.org # v4.12 > Signed-off-by: Hauke Mehrtens Series applied to mips-fixes. Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paul.burton@mips.com to report it. ]