From: "H. Nikolaus Schaller" <hns@goldelico.com>
To: Paul Cercueil <paul@crapouillou.net>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
"H. Nikolaus Schaller" <hns@goldelico.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Kees Cook <keescook@chromium.org>,
"Eric W. Biederman" <ebiederm@xmission.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Robert Foss <robert.foss@linaro.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Ezequiel Garcia <ezequiel@collabora.com>,
Harry Wentland <harry.wentland@amd.com>,
Sam Ravnborg <sam@ravnborg.org>,
Maxime Ripard <maxime@cerno.tech>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>
Cc: devicetree@vger.kernel.org, linux-mips@vger.kernel.org,
linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org,
Paul Boddie <paul@boddie.org.uk>, Jonas Karlman <jonas@kwiboo.se>,
dri-devel@lists.freedesktop.org
Subject: [PATCH v3 9/9] drm/ingenic: add some jz4780 specific features
Date: Sun, 8 Aug 2021 07:10:43 +0200 [thread overview]
Message-ID: <aebcc6c5340f755268af268725939b1e59a83472.1628399442.git.hns@goldelico.com> (raw)
In-Reply-To: <cover.1628399442.git.hns@goldelico.com>
From: Paul Boddie <paul@boddie.org.uk>
The jz4780 has some features which need initialization
according to the vendor kernel.
Signed-off-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 39 +++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 33ce3794aa126..f3b1b10bc079b 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -69,6 +69,10 @@ struct jz_soc_info {
bool needs_dev_clk;
bool has_osd;
bool map_noncoherent;
+ bool has_alpha;
+ bool has_pcfg;
+ bool has_recover;
+ bool has_rgbc;
bool use_extended_hwdesc;
unsigned int hwdesc_size;
unsigned int max_width, max_height;
@@ -671,6 +675,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
| JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
}
+ if (priv->soc_info->has_recover)
+ cfg |= JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN;
+
/* set use of the 8-word descriptor and OSD foreground usage. */
if (priv->soc_info->use_extended_hwdesc)
cfg |= JZ_LCD_CFG_DESCRIPTOR_8;
@@ -1208,6 +1215,25 @@ static int ingenic_drm_bind(struct device *dev, bool has_components)
if (soc_info->has_osd)
regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN);
+ if (soc_info->has_alpha)
+ regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_ALPHAEN);
+
+ /* Magic values from the vendor kernel for the priority thresholds. */
+ if (soc_info->has_pcfg)
+ regmap_write(priv->map, JZ_REG_LCD_PCFG,
+ JZ_LCD_PCFG_PRI_MODE |
+ JZ_LCD_PCFG_HP_BST_16 |
+ (511 << JZ_LCD_PCFG_THRESHOLD2_OFFSET) |
+ (400 << JZ_LCD_PCFG_THRESHOLD1_OFFSET) |
+ (256 << JZ_LCD_PCFG_THRESHOLD0_OFFSET));
+
+ /* RGB output control may be superfluous. */
+ if (soc_info->has_rgbc)
+ regmap_write(priv->map, JZ_REG_LCD_RGBC,
+ JZ_LCD_RGBC_RGB_FORMAT_ENABLE |
+ JZ_LCD_RGBC_ODD_RGB |
+ JZ_LCD_RGBC_EVEN_RGB);
+
mutex_init(&priv->clk_mutex);
priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;
@@ -1355,6 +1381,9 @@ static const struct jz_soc_info jz4740_soc_info = {
.needs_dev_clk = true,
.has_osd = false,
.map_noncoherent = false,
+ .has_pcfg = false,
+ .has_recover = false,
+ .has_rgbc = false,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc),
.max_width = 800,
.max_height = 600,
@@ -1368,6 +1397,9 @@ static const struct jz_soc_info jz4725b_soc_info = {
.needs_dev_clk = false,
.has_osd = true,
.map_noncoherent = false,
+ .has_pcfg = false,
+ .has_recover = false,
+ .has_rgbc = false,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc),
.max_width = 800,
.max_height = 600,
@@ -1382,6 +1414,9 @@ static const struct jz_soc_info jz4770_soc_info = {
.needs_dev_clk = false,
.has_osd = true,
.map_noncoherent = true,
+ .has_pcfg = false,
+ .has_recover = false,
+ .has_rgbc = false,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc),
.max_width = 1280,
.max_height = 720,
@@ -1395,6 +1430,10 @@ static const struct jz_soc_info jz4770_soc_info = {
static const struct jz_soc_info jz4780_soc_info = {
.needs_dev_clk = true,
.has_osd = true,
+ .has_alpha = true,
+ .has_pcfg = true,
+ .has_recover = true,
+ .has_rgbc = true,
.use_extended_hwdesc = true,
.hwdesc_size = sizeof(struct ingenic_dma_hwdesc_ext),
.max_width = 4096,
--
2.31.1
prev parent reply other threads:[~2021-08-08 5:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-08 5:10 [PATCH v3 0/9] MIPS: JZ4780 and CI20 HDMI H. Nikolaus Schaller
2021-08-08 5:10 ` [PATCH v3 1/9] drm/ingenic: fix drm_init error path if IPU was registered H. Nikolaus Schaller
2021-08-08 5:10 ` [PATCH v3 2/9] drm/bridge: synopsis: Add mode_fixup and bridge timings support H. Nikolaus Schaller
2021-08-08 5:10 ` [PATCH v3 3/9] drm/ingenic: Add jz4780 Synopsys HDMI driver H. Nikolaus Schaller
2021-08-08 5:10 ` [PATCH v3 4/9] drm/ingenic: Add support for JZ4780 and HDMI output H. Nikolaus Schaller
2021-08-08 5:10 ` [PATCH v3 5/9] dt-bindings: display: Add ingenic-jz4780-hdmi DT Schema H. Nikolaus Schaller
2021-08-13 20:46 ` Rob Herring
2021-08-08 5:10 ` [PATCH v3 6/9] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controllers H. Nikolaus Schaller
2021-08-08 5:10 ` [PATCH v3 7/9] MIPS: DTS: CI20: add HDMI setup H. Nikolaus Schaller
2021-08-08 5:10 ` [PATCH v3 8/9] MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780 H. Nikolaus Schaller
2021-08-08 5:10 ` H. Nikolaus Schaller [this message]
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