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Date:   Fri, 31 Mar 2017 11:02:33 +0200 (CEST)
From:   Thomas Gleixner <tglx@linutronix.de>
To:     Paul Burton <paul.burton@imgtec.com>
cc:     Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org,
        Marc Zyngier <marc.zyngier@arm.com>,
        Jason Cooper <jason@lakedaemon.net>
Subject: Re: [PATCH 0/5] MIPS/irqchip: Use IPI IRQ domains for CPU interrupt
 controller IPIs
In-Reply-To: <20170330190614.14844-1-paul.burton@imgtec.com>
Message-ID: <alpine.DEB.2.20.1703311101340.1780@nanos>
References: <20170330190614.14844-1-paul.burton@imgtec.com>
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On Thu, 30 Mar 2017, Paul Burton wrote:

> This series introduces support for IPI IRQ domains to the CPU interrupt
> controller driver, allowing IPIs to function in the same way as those
> provided by the MIPS GIC as far as platform/board code is concerned.
> 
> Doing this allows us to avoid duplicating code across platforms, avoid
> having to handle cases where IPI domains are or aren't in use depending
> upon the interrupt controller, and strengthen a sanity check for cases
> where IPI IRQ domains are supported.

For the irqchip parts:

Acked-by: Thomas Gleixner <tglx@linutronix.de>

Ralf, feel free to route the whole lot through your MIPS tree.

Thanks,

	tglx