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* [PATCHv2] mips: Do not include hi and lo in clobber list for R6
@ 2020-07-25 14:54 Romain Naour
  2020-07-31 19:02 ` Maciej W. Rozycki
  0 siblings, 1 reply; 2+ messages in thread
From: Romain Naour @ 2020-07-25 14:54 UTC (permalink / raw)
  To: linux-mips; +Cc: Romain Naour

From [1]
"GCC 10 (PR 91233) won't silently allow registers that are not architecturally
available to be present in the clobber list anymore, resulting in build failure
for mips*r6 targets in form of:
...
.../sysdep.h:146:2: error: the register ‘lo’ cannot be clobbered in ‘asm’ for the current target
  146 |  __asm__ volatile (      \
      |  ^~~~~~~

This is because base R6 ISA doesn't define hi and lo registers w/o DSP extension.
This patch provides the alternative clobber list for r6 targets that won't include
those registers."

Since kernel 5.4 and mips support for generic vDSO [2], the kernel fail to build
for mips r6 cpus with gcc 10 for the same reason as glibc.

[1] https://sourceware.org/git/?p=glibc.git;a=commit;h=020b2a97bb15f807c0482f0faee2184ed05bcad8
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=24640f233b466051ad3a5d2786d2951e43026c9d

Signed-off-by: Romain Naour <romain.naour@gmail.com>
---
v2 use MIPS_ISA_REV instead of __mips_isa_rev (Alexander Lobakin)
---
 arch/mips/include/asm/vdso/gettimeofday.h | 45 +++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/mips/include/asm/vdso/gettimeofday.h b/arch/mips/include/asm/vdso/gettimeofday.h
index c63ddcaea54c..e377a7201a33 100644
--- a/arch/mips/include/asm/vdso/gettimeofday.h
+++ b/arch/mips/include/asm/vdso/gettimeofday.h
@@ -30,12 +30,21 @@ static __always_inline long gettimeofday_fallback(
 	register long nr asm("v0") = __NR_gettimeofday;
 	register long error asm("a3");
 
+#if MIPS_ISA_REV >= 6
+	asm volatile(
+	"       syscall\n"
+	: "=r" (ret), "=r" (error)
+	: "r" (tv), "r" (tz), "r" (nr)
+	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+	  "$14", "$15", "$24", "$25", "memory");
+#else
 	asm volatile(
 	"       syscall\n"
 	: "=r" (ret), "=r" (error)
 	: "r" (tv), "r" (tz), "r" (nr)
 	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
 	  "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+#endif
 
 	return error ? -ret : ret;
 }
@@ -54,12 +63,21 @@ static __always_inline long clock_gettime_fallback(
 #endif
 	register long error asm("a3");
 
+#if MIPS_ISA_REV >= 6
+	asm volatile(
+	"       syscall\n"
+	: "=r" (ret), "=r" (error)
+	: "r" (clkid), "r" (ts), "r" (nr)
+	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+	  "$14", "$15", "$24", "$25", "memory");
+#else
 	asm volatile(
 	"       syscall\n"
 	: "=r" (ret), "=r" (error)
 	: "r" (clkid), "r" (ts), "r" (nr)
 	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
 	  "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+#endif
 
 	return error ? -ret : ret;
 }
@@ -78,12 +96,21 @@ static __always_inline int clock_getres_fallback(
 #endif
 	register long error asm("a3");
 
+#if MIPS_ISA_REV >= 6
+	asm volatile(
+	"       syscall\n"
+	: "=r" (ret), "=r" (error)
+	: "r" (clkid), "r" (ts), "r" (nr)
+	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+	  "$14", "$15", "$24", "$25", "memory");
+#else
 	asm volatile(
 	"       syscall\n"
 	: "=r" (ret), "=r" (error)
 	: "r" (clkid), "r" (ts), "r" (nr)
 	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
 	  "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+#endif
 
 	return error ? -ret : ret;
 }
@@ -100,12 +127,21 @@ static __always_inline long clock_gettime32_fallback(
 	register long nr asm("v0") = __NR_clock_gettime;
 	register long error asm("a3");
 
+#if MIPS_ISA_REV >= 6
+	asm volatile(
+	"       syscall\n"
+	: "=r" (ret), "=r" (error)
+	: "r" (clkid), "r" (ts), "r" (nr)
+	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+	  "$14", "$15", "$24", "$25", "memory");
+#else
 	asm volatile(
 	"       syscall\n"
 	: "=r" (ret), "=r" (error)
 	: "r" (clkid), "r" (ts), "r" (nr)
 	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
 	  "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+#endif
 
 	return error ? -ret : ret;
 }
@@ -120,12 +156,21 @@ static __always_inline int clock_getres32_fallback(
 	register long nr asm("v0") = __NR_clock_getres;
 	register long error asm("a3");
 
+#if MIPS_ISA_REV >= 6
+	asm volatile(
+	"       syscall\n"
+	: "=r" (ret), "=r" (error)
+	: "r" (clkid), "r" (ts), "r" (nr)
+	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+	  "$14", "$15", "$24", "$25", "memory");
+#else
 	asm volatile(
 	"       syscall\n"
 	: "=r" (ret), "=r" (error)
 	: "r" (clkid), "r" (ts), "r" (nr)
 	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
 	  "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+#endif
 
 	return error ? -ret : ret;
 }
-- 
2.25.4


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCHv2] mips: Do not include hi and lo in clobber list for R6
  2020-07-25 14:54 [PATCHv2] mips: Do not include hi and lo in clobber list for R6 Romain Naour
@ 2020-07-31 19:02 ` Maciej W. Rozycki
  0 siblings, 0 replies; 2+ messages in thread
From: Maciej W. Rozycki @ 2020-07-31 19:02 UTC (permalink / raw)
  To: Romain Naour; +Cc: linux-mips, Maciej W. Rozycki

On Sat, 25 Jul 2020, Romain Naour wrote:

> diff --git a/arch/mips/include/asm/vdso/gettimeofday.h b/arch/mips/include/asm/vdso/gettimeofday.h
> index c63ddcaea54c..e377a7201a33 100644
> --- a/arch/mips/include/asm/vdso/gettimeofday.h
> +++ b/arch/mips/include/asm/vdso/gettimeofday.h
> @@ -30,12 +30,21 @@ static __always_inline long gettimeofday_fallback(
>  	register long nr asm("v0") = __NR_gettimeofday;
>  	register long error asm("a3");
>  
> +#if MIPS_ISA_REV >= 6
> +	asm volatile(
> +	"       syscall\n"
> +	: "=r" (ret), "=r" (error)
> +	: "r" (tv), "r" (tz), "r" (nr)
> +	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
> +	  "$14", "$15", "$24", "$25", "memory");
> +#else
>  	asm volatile(
>  	"       syscall\n"
>  	: "=r" (ret), "=r" (error)
>  	: "r" (tv), "r" (tz), "r" (nr)
>  	: "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
>  	  "$14", "$15", "$24", "$25", "hi", "lo", "memory");
> +#endif

 Argh, please avoid a flood of inline #ifdef's across code; let alone 
repeating identical parts in both legs of the conditional.

 We've been through this before, cf. commit b0984c43702f ("MIPS: Fix 
microMIPS LL/SC immediate offsets"), or commit 09abbcffb3ee ("[MIPS] 
cpu-bugs64.c: GCC 3.3 constraint workaround"), or the GCC_REG_ACCUM macro 
visible in the latter commit (originally added with historical commit 
f4232a2ce8f9 reachable at <git://git.linux-mips.org/pub/scm/ralf/linux> if 
you can have a look there).

  Maciej

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2020-07-25 14:54 [PATCHv2] mips: Do not include hi and lo in clobber list for R6 Romain Naour
2020-07-31 19:02 ` Maciej W. Rozycki

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