From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 263DCC433E0 for ; Sat, 9 Jan 2021 20:03:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D935D238E7 for ; Sat, 9 Jan 2021 20:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726005AbhAIUCu (ORCPT ); Sat, 9 Jan 2021 15:02:50 -0500 Received: from [78.8.192.131] ([78.8.192.131]:12716 "EHLO orcam.me.uk" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725999AbhAIUCu (ORCPT ); Sat, 9 Jan 2021 15:02:50 -0500 X-Greylist: delayed 504 seconds by postgrey-1.27 at vger.kernel.org; Sat, 09 Jan 2021 15:02:49 EST Received: from cvs.linux-mips.org (eddie.linux-mips.org [148.251.95.138]) by orcam.me.uk (Postfix) with ESMTPS id D7E412BE0EC; Sat, 9 Jan 2021 19:53:52 +0000 (GMT) Date: Sat, 9 Jan 2021 19:53:19 +0000 (GMT) From: "Maciej W. Rozycki" To: Aurelien Jarno cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, YunQiang Su , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang , "open list:MIPS" Subject: Re: [PATCH] MIPS: Support binutils configured with --enable-mips-fix-loongson3-llsc=yes In-Reply-To: <20210109193048.478339-1-aurelien@aurel32.net> Message-ID: References: <20210109193048.478339-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Sat, 9 Jan 2021, Aurelien Jarno wrote: > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index cd4343edeb11..5ffdd67093bc 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -136,6 +136,25 @@ cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ > # > cflags-y += -fno-stack-check > > +# binutils from v2.35 when built with --enable-mips-fix-loongson3-llsc=yes, > +# supports an -mfix-loongson3-llsc flag which emits a sync prior to each ll > +# instruction to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h > +# for a description). > +# > +# We disable this in order to prevent the assembler meddling with the > +# instruction that labels refer to, ie. if we label an ll instruction: > +# > +# 1: ll v0, 0(a0) > +# > +# ...then with the assembler fix applied the label may actually point at a sync > +# instruction inserted by the assembler, and if we were using the label in an > +# exception table the table would no longer contain the address of the ll > +# instruction. Interesting. Given that a MIPS assembler is generally free to shuffle instructions as it sees fit in its default reorder mode as long as that does not change the semantics of the code executed, shouldn't we instead place all label/instruction pairs used for exception handling in noreorder blocks so as to make sure the label refers to the instruction an exception handler expects it to? E.g. for the case quoted above: .set push .set noreorder 1: ll v0, 0(a0) .set pop Maciej