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[88.10.102.251]) by smtp.gmail.com with ESMTPSA id c8sm11769791wrn.50.2019.09.01.15.53.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Sep 2019 15:53:09 -0700 (PDT) Subject: Re: [PATCH] MIPS: Drop Loongson _CACHE_* definitions To: Paul Burton , "linux-mips@vger.kernel.org" Cc: Paul Burton , Huacai Chen References: <20190831154145.7328-1-paul.burton@mips.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: url=http://pgp.mit.edu/pks/lookup?op=get&search=0xE3E32C2CDEADC0DE Message-ID: Date: Mon, 2 Sep 2019 00:53:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190831154145.7328-1-paul.burton@mips.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On 8/31/19 5:41 PM, Paul Burton wrote: > _CACHE_CACHABLE_NONCOHERENT is defined as 3<<_CACHE_SHIFT by default, so > there's no need to define it as such specifically for Loongson. > > _CACHE_CACHABLE_COHERENT is not used anywhere in the kernel, so there's > no need to define it at all. > > Finally the comment found alongside these definitions seems incorrect - > it suggests that we're defining _CACHE_CACHABLE_NONCOHERENT such that it > actually provides coherence, but the opposite seems to be true & instead > the unused _CACHE_CACHABLE_COHERENT is defined as the typically > incoherent value. > > Delete the whole thing, which will have no effect on the compiled code > anyway. > > Signed-off-by: Paul Burton > Cc: Huacai Chen > --- > > arch/mips/include/asm/pgtable-bits.h | 7 ------- > 1 file changed, 7 deletions(-) > > diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h > index 5f1ced8cba07..409ae01ed7be 100644 > --- a/arch/mips/include/asm/pgtable-bits.h > +++ b/arch/mips/include/asm/pgtable-bits.h > @@ -221,13 +221,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) > > #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) > > -#elif defined(CONFIG_CPU_LOONGSON3) > - > -/* Using COHERENT flag for NONCOHERENT doesn't hurt. */ > - > -#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ > -#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ > - > #elif defined(CONFIG_MACH_INGENIC) > > /* Ingenic uses the WA bit to achieve write-combine memory writes */ > Reviewed-by: Philippe Mathieu-Daudé