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* [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC
@ 2020-06-17 22:31 Serge Semin
  2020-06-17 22:31 ` [PATCH v4 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
                   ` (5 more replies)
  0 siblings, 6 replies; 11+ messages in thread
From: Serge Semin @ 2020-06-17 22:31 UTC (permalink / raw)
  To: Thomas Gleixner, Rafael J. Wysocki, Daniel Lezcano,
	Thomas Bogendoerfer, Greg Kroah-Hartman
  Cc: Serge Semin, Serge Semin, Alexey Malahov, Rob Herring,
	Arnd Bergmann, Jason Cooper, Marc Zyngier, James Hogan,
	linux-mips, devicetree, linux-kernel

Daniel, Rafael, Thomas (Gleixner), could you specifically take a look at
the last patch in this series? If you are ok with that, please explicitly
ack. We need at least one of your blessing to merge the series in, since
the code and DT-related patches here have been mostly reviewed. We've
missed the last merge window. It would be pity to miss the next one...

Regarding this patchset origin. Recently I've submitted a series of
patchset's which provided multiple fixes for the MIPS arch subsystem and
the MIPS GIC and DW APB Timer drivers, which were required for the
Baikal-T1 SoC correctly working with those drivers. Mostly those patchsets
have been already merged into the corresponding subsystems, but several
patches have been left floating since noone really responded for review
except Rob provided his approval regarding DT bindings. Thus in this
patchset I've collected all the leftovers so not to loose them in a pale
of the maintainers email logs.

The patchset includes the following updates: MIPS CPC and GIC DT bindings
legacy text-based file are converted to the DT schema (Rob has already
reviewed them), add MIPS CDMM DT node support to place the CDMM block at
the platform-specific MMIO range, make sure MIPS CDMM is available for
MIPS_R5 CPUs.

Seeing the series concerns the MIPS-related drivers it's better to merge
it in through the MIPS repository:
https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/

This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
base-commit: 0e698dfa2822 ("Linux 5.7-rc4")
tag: v5.7-rc4

Suggestion.
Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
been seen maintaining MIPS for a long time, Thomas is only responsible
for the next part of it:
	F:      Documentation/devicetree/bindings/mips/
	F:      Documentation/mips/
	F:      arch/mips/
	F:      drivers/platform/mips/
the MIPS-specific drivers like:
	F:	drivers/bus/mips_cdmm.c
	F:	drivers/irqchip/irq-mips-cpu.c
	F:	drivers/irqchip/irq-mips-gic.c
	F:	drivers/clocksource/mips-gic-timer.c
	F:	drivers/cpuidle/cpuidle-cps.c
seem to be left for the subsystems maintainers to support. So if you don't
mind or unless there is a better alternative, I can help with looking
after them to ease the maintainers review burden and since I'll be working
on our MIPS-based SoC drivers integrating into the mainline kernel repo
anyway. Thomas agreed to join in maintaining that drivers.

Previous patchsets:
mips: Prepare MIPS-arch code for Baikal-T1 SoC support:
Link: https://lore.kernel.org/linux-mips/20200306124807.3596F80307C2@mail.baikalelectronics.ru
Link: https://lore.kernel.org/linux-mips/20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-mips/20200521140725.29571-1-Sergey.Semin@baikalelectronics.ru

clocksource: Fix MIPS GIC and DW APB Timer for Baikal-T1 SoC support:
Link: https://lore.kernel.org/linux-rtc/20200324174325.14213-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-rtc/20200506214107.25956-1-Sergey.Semin@baikalelectronics.ru
Link: https://lore.kernel.org/linux-rtc/20200521005321.12129-1-Sergey.Semin@baikalelectronics.ru

Changelog prev:
- Add yaml-based bindings file for MIPS CDMM dt-node.
- Convert mti,mips-cpc to DT schema.
- Use a shorter summary describing the bindings modification patches.
- Rearrange the SoBs with adding Alexey' co-development tag.
- Lowercase the hex numbers in the dt-bindings.

Changelog v2:
- Resend.

Link: https://lore.kernel.org/linux-mips/20200601122121.15809-1-Sergey.Semin@baikalelectronics.ru
Changelog v3:
- Keep F: MAINTAINERS section alphabetically ordered.
- Add Thomas as the co-maintainer of the MIPS CPU and GIC IRQchip, MIPS
  GIC timer and MIPS CPS CPUidle drivers.

Link: https://lore.kernel.org/linux-mips/20200602100921.1155-1-Sergey.Semin@baikalelectronics.ru
Changelog v4:
- Resend.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Serge Semin (6):
  dt-bindings: power: Convert mti,mips-cpc to DT schema
  dt-bindings: interrupt-controller: Convert mti,gic to DT schema
  dt-bindings: bus: Add MIPS CDMM controller
  mips: cdmm: Add mti,mips-cdmm dtb node support
  bus: cdmm: Add MIPS R5 arch support
  MAINTAINERS: Add maintainers for MIPS core drivers

 .../bindings/bus/mti,mips-cdmm.yaml           |  35 +++++
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 .../bindings/power/mti,mips-cpc.txt           |   8 -
 .../bindings/power/mti,mips-cpc.yaml          |  35 +++++
 MAINTAINERS                                   |  11 ++
 drivers/bus/Kconfig                           |   2 +-
 drivers/bus/mips_cdmm.c                       |  15 ++
 8 files changed, 245 insertions(+), 76 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
 delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt
 create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml

-- 
2.26.2


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH v4 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema
  2020-06-17 22:31 [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
@ 2020-06-17 22:31 ` Serge Semin
  2020-06-29 21:46   ` Rob Herring
  2020-06-17 22:31 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Convert mti,gic " Serge Semin
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 11+ messages in thread
From: Serge Semin @ 2020-06-17 22:31 UTC (permalink / raw)
  To: Thomas Gleixner, Rafael J. Wysocki, Daniel Lezcano,
	Thomas Bogendoerfer, Greg Kroah-Hartman, Paul Burton,
	Rob Herring
  Cc: Serge Semin, Serge Semin, Rob Herring, Alexey Malahov,
	linux-mips, devicetree, linux-kernel

It's a Cluster Power Controller embedded into the MIPS IP cores.
Currently the corresponding dts node is supposed to have compatible
and reg properties.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>

---

Changelog prev:
- Reword the changelog summary - use shorter version.
- Lowercase the example hex'es.
---
 .../bindings/power/mti,mips-cpc.txt           |  8 -----
 .../bindings/power/mti,mips-cpc.yaml          | 35 +++++++++++++++++++
 2 files changed, 35 insertions(+), 8 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt
 create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml

diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt
deleted file mode 100644
index c6b82511ae8a..000000000000
--- a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Binding for MIPS Cluster Power Controller (CPC).
-
-This binding allows a system to specify where the CPC registers are
-located.
-
-Required properties:
-compatible : Should be "mti,mips-cpc".
-regs: Should describe the address & size of the CPC register region.
diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml
new file mode 100644
index 000000000000..9cd92a57130c
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Cluster Power Controller
+
+description: |
+  Defines a location of the MIPS Cluster Power Controller registers.
+
+maintainers:
+  - Paul Burton <paulburton@kernel.org>
+
+properties:
+  compatible:
+    const: mti,mips-cpc
+
+  reg:
+    description: |
+      Base address and size of an unoccupied memory region, which will be
+      used to map the MIPS CPC registers block.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    cpc@1bde0000 {
+      compatible = "mti,mips-cpc";
+      reg = <0 0x1bde0000 0 0x8000>;
+    };
+...
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v4 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema
  2020-06-17 22:31 [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
  2020-06-17 22:31 ` [PATCH v4 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
@ 2020-06-17 22:31 ` Serge Semin
  2020-06-17 22:31 ` [PATCH v4 3/6] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 11+ messages in thread
From: Serge Semin @ 2020-06-17 22:31 UTC (permalink / raw)
  To: Thomas Gleixner, Rafael J. Wysocki, Daniel Lezcano,
	Thomas Bogendoerfer, Greg Kroah-Hartman, Jason Cooper,
	Marc Zyngier, Rob Herring
  Cc: Serge Semin, Serge Semin, Rob Herring, Alexey Malahov,
	linux-mips, linux-kernel, devicetree

Modern device tree bindings are supposed to be created as YAML-files
in accordance with DT schema. This commit replaces MIPS GIC legacy bare
text binding with YAML file. As before the binding file states that the
corresponding dts node is supposed to be compatible with MIPS Global
Interrupt Controller indicated by the "mti,gic" compatible string and
to provide a mandatory interrupt-controller and '#interrupt-cells'
properties. There might be optional registers memory range,
"mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties
specified.

MIPS GIC also includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Since currently the GIC Timer is only supported the
DT schema expects an IRQ and clock-phandler charged timer sub-node with
"mti,mips-gic-timer" compatible string.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: linux-mips@vger.kernel.org

---

I don't really know who is the corresponding driver maintainer, so I
added Paul to the maintainers property since he used to be looking for the
MIPS arch and Thomas looking after it now. Any idea what email should be
specified there instead?

Changelog prev:
- Since timer sub-node has no unit-address, the node shouldn't be named
  with one. So alter the MIPS GIC bindings to have a pure "timer"
  sub-node.
- Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ].
- Since it's a conversion patch use GPL-2.0-only SPDX header.
---
 .../interrupt-controller/mips-gic.txt         |  67 --------
 .../interrupt-controller/mti,gic.yaml         | 148 ++++++++++++++++++
 2 files changed, 148 insertions(+), 67 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
deleted file mode 100644
index 173595305e26..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-MIPS Global Interrupt Controller (GIC)
-
-The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
-It also supports local (per-processor) interrupts and software-generated
-interrupts which can be used as IPIs.  The GIC also includes a free-running
-global timer, per-CPU count/compare timers, and a watchdog.
-
-Required properties:
-- compatible : Should be "mti,gic".
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt specifier.  Should be 3.
-  - The first cell is the type of interrupt, local or shared.
-    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
-  - The second cell is the GIC interrupt number.
-  - The third cell encodes the interrupt flags.
-    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
-    flags.
-
-Optional properties:
-- reg : Base address and length of the GIC registers.  If not present,
-  the base address reported by the hardware GCR_GIC_BASE will be used.
-- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
-  to which the GIC may not route interrupts.  Valid values are 2 - 7.
-  This property is ignored if the CPU is started in EIC mode.
-- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
-  reserved for IPIs.
-  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
-  of the reserved range.
-  If not specified, the driver will allocate the last 2 * number of VPEs in the
-  system.
-
-Required properties for timer sub-node:
-- compatible : Should be "mti,gic-timer".
-- interrupts : Interrupt for the GIC local timer.
-
-Optional properties for timer sub-node:
-- clocks : GIC timer operating clock.
-- clock-frequency : Clock frequency at which the GIC timers operate.
-
-Note that one of clocks or clock-frequency must be specified.
-
-Example:
-
-	gic: interrupt-controller@1bdc0000 {
-		compatible = "mti,gic";
-		reg = <0x1bdc0000 0x20000>;
-
-		interrupt-controller;
-		#interrupt-cells = <3>;
-
-		mti,reserved-cpu-vectors = <7>;
-		mti,reserved-ipi-vectors = <40 8>;
-
-		timer {
-			compatible = "mti,gic-timer";
-			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-			clock-frequency = <50000000>;
-		};
-	};
-
-	uart@18101400 {
-		...
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-		...
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
new file mode 100644
index 000000000000..9f0eb3addac4
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Global Interrupt Controller
+
+maintainers:
+  - Paul Burton <paulburton@kernel.org>
+  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description: |
+  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+  It also supports local (per-processor) interrupts and software-generated
+  interrupts which can be used as IPIs. The GIC also includes a free-running
+  global timer, per-CPU count/compare timers, and a watchdog.
+
+properties:
+  compatible:
+    const: mti,gic
+
+  "#interrupt-cells":
+    const: 3
+    description: |
+      The 1st cell is the type of interrupt: local or shared defined in the
+      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
+      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
+      the IRQ trigger modes, which are defined in the file
+      'dt-bindings/interrupt-controller/irq.h'.
+
+  reg:
+    description: |
+      Base address and length of the GIC registers space. If not present,
+      the base address reported by the hardware GCR_GIC_BASE will be used.
+    maxItems: 1
+
+  interrupt-controller: true
+
+  mti,reserved-cpu-vectors:
+    description: |
+      Specifies the list of CPU interrupt vectors to which the GIC may not
+      route interrupts. This property is ignored if the CPU is started in EIC
+      mode.
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - minItems: 1
+        maxItems: 6
+        uniqueItems: true
+        items:
+          minimum: 2
+          maximum: 7
+
+  mti,reserved-ipi-vectors:
+    description: |
+      Specifies the range of GIC interrupts that are reserved for IPIs.
+      It accepts two values: the 1st is the starting interrupt and the 2nd is
+      the size of the reserved range. If not specified, the driver will
+      allocate the last (2 * number of VPEs in the system).
+    allOf:
+      - $ref: /schemas/types.yaml#definitions/uint32-array
+      - items:
+          - minimum: 0
+            maximum: 254
+          - minimum: 2
+            maximum: 254
+
+  timer:
+    type: object
+    description: |
+      MIPS GIC includes a free-running global timer, per-CPU count/compare
+      timers, and a watchdog. Currently only the GIC Timer is supported.
+    properties:
+      compatible:
+        const: mti,gic-timer
+
+      interrupts:
+        description: |
+          Interrupt for the GIC local timer, so normally it's suppose to be of
+          <GIC_LOCAL X IRQ_TYPE_NONE> format.
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      clock-frequency: true
+
+    required:
+      - compatible
+      - interrupts
+
+    oneOf:
+      - required:
+          - clocks
+      - required:
+          - clock-frequency
+
+    additionalProperties: false
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - "#interrupt-cells"
+  - interrupt-controller
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+      mti,reserved-cpu-vectors = <7>;
+      mti,reserved-ipi-vectors = <40 8>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clock-frequency = <50000000>;
+      };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/mips-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    interrupt-controller@1bdc0000 {
+      compatible = "mti,gic";
+      reg = <0x1bdc0000 0x20000>;
+      interrupt-controller;
+      #interrupt-cells = <3>;
+
+      timer {
+        compatible = "mti,gic-timer";
+        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+        clocks = <&cpu_pll>;
+      };
+    };
+  - |
+    interrupt-controller {
+      compatible = "mti,gic";
+      interrupt-controller;
+      #interrupt-cells = <3>;
+    };
+...
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v4 3/6] dt-bindings: bus: Add MIPS CDMM controller
  2020-06-17 22:31 [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
  2020-06-17 22:31 ` [PATCH v4 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
  2020-06-17 22:31 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Convert mti,gic " Serge Semin
@ 2020-06-17 22:31 ` Serge Semin
  2020-06-29 21:46   ` Rob Herring
  2020-06-17 22:31 ` [PATCH v4 4/6] mips: cdmm: Add mti,mips-cdmm dtb node support Serge Semin
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 11+ messages in thread
From: Serge Semin @ 2020-06-17 22:31 UTC (permalink / raw)
  To: Thomas Gleixner, Rafael J. Wysocki, Daniel Lezcano,
	Thomas Bogendoerfer, Greg Kroah-Hartman, Rob Herring
  Cc: Serge Semin, Serge Semin, Rob Herring, Alexey Malahov,
	linux-mips, devicetree, linux-kernel

It's a Common Device Memory Map controller embedded into the MIPS IP
cores, which dts node is supposed to have compatible and reg properties.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: linux-mips@vger.kernel.org

---

Changelog prev:
- Lowercase the example hex'es.
---
 .../bindings/bus/mti,mips-cdmm.yaml           | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml

diff --git a/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
new file mode 100644
index 000000000000..b3ba98515cbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Common Device Memory Map
+
+description: |
+  Defines a location of the MIPS Common Device Memory Map registers.
+
+maintainers:
+  - James Hogan <jhogan@kernel.org>
+
+properties:
+  compatible:
+    const: mti,mips-cdmm
+
+  reg:
+    description: |
+      Base address and size of an unoccupied memory region, which will be
+      used to map the MIPS CDMM registers block.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    cdmm@1bde8000 {
+      compatible = "mti,mips-cdmm";
+      reg = <0 0x1bde8000 0 0x8000>;
+    };
+...
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v4 4/6] mips: cdmm: Add mti,mips-cdmm dtb node support
  2020-06-17 22:31 [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
                   ` (2 preceding siblings ...)
  2020-06-17 22:31 ` [PATCH v4 3/6] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
@ 2020-06-17 22:31 ` Serge Semin
  2020-06-17 22:31 ` [PATCH v4 5/6] bus: cdmm: Add MIPS R5 arch support Serge Semin
  2020-06-17 22:32 ` [PATCH v4 6/6] MAINTAINERS: Add maintainers for MIPS core drivers Serge Semin
  5 siblings, 0 replies; 11+ messages in thread
From: Serge Semin @ 2020-06-17 22:31 UTC (permalink / raw)
  To: Thomas Gleixner, Rafael J. Wysocki, Daniel Lezcano,
	Thomas Bogendoerfer, Greg Kroah-Hartman, Serge Semin
  Cc: Serge Semin, Alexey Malahov, devicetree, linux-mips, linux-kernel

Since having and mapping the CDMM block is platform specific, then
instead of just returning a zero-address, lets make the default CDMM
base address search method (mips_cdmm_phys_base()) to do something
useful. For instance to find the address in a dedicated dtb-node in
order to support of-based platforms by default.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: devicetree@vger.kernel.org

---

Changelog prev:
- Use alphabetical order for the include pre-processor operator.
---
 drivers/bus/mips_cdmm.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c
index 1b14256376d2..9f7ed1fcd428 100644
--- a/drivers/bus/mips_cdmm.c
+++ b/drivers/bus/mips_cdmm.c
@@ -13,6 +13,8 @@
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/smp.h>
@@ -337,9 +339,22 @@ static phys_addr_t mips_cdmm_cur_base(void)
  * Picking a suitable physical address at which to map the CDMM region is
  * platform specific, so this weak function can be overridden by platform
  * code to pick a suitable value if none is configured by the bootloader.
+ * By default this method tries to find a CDMM-specific node in the system
+ * dtb. Note that this won't work for early serial console.
  */
 phys_addr_t __weak mips_cdmm_phys_base(void)
 {
+	struct device_node *np;
+	struct resource res;
+	int err;
+
+	np = of_find_compatible_node(NULL, NULL, "mti,mips-cdmm");
+	if (np) {
+		err = of_address_to_resource(np, 0, &res);
+		if (!err)
+			return res.start;
+	}
+
 	return 0;
 }
 
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v4 5/6] bus: cdmm: Add MIPS R5 arch support
  2020-06-17 22:31 [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
                   ` (3 preceding siblings ...)
  2020-06-17 22:31 ` [PATCH v4 4/6] mips: cdmm: Add mti,mips-cdmm dtb node support Serge Semin
@ 2020-06-17 22:31 ` Serge Semin
  2020-06-17 22:32 ` [PATCH v4 6/6] MAINTAINERS: Add maintainers for MIPS core drivers Serge Semin
  5 siblings, 0 replies; 11+ messages in thread
From: Serge Semin @ 2020-06-17 22:31 UTC (permalink / raw)
  To: Thomas Gleixner, Rafael J. Wysocki, Daniel Lezcano,
	Thomas Bogendoerfer, Greg Kroah-Hartman
  Cc: Serge Semin, Serge Semin, Alexey Malahov, linux-mips, devicetree,
	linux-kernel

CDMM may be available not only on MIPS R2 architectures, but also on
newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark
the CDMM bus being supported for that MIPS arch too.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
 drivers/bus/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 6d4e4497b59b..971c07bc92d4 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -58,7 +58,7 @@ config IMX_WEIM
 
 config MIPS_CDMM
 	bool "MIPS Common Device Memory Map (CDMM) Driver"
-	depends on CPU_MIPSR2
+	depends on CPU_MIPSR2 || CPU_MIPSR5
 	help
 	  Driver needed for the MIPS Common Device Memory Map bus in MIPS
 	  cores. This bus is for per-CPU tightly coupled devices such as the
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* [PATCH v4 6/6] MAINTAINERS: Add maintainers for MIPS core drivers
  2020-06-17 22:31 [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
                   ` (4 preceding siblings ...)
  2020-06-17 22:31 ` [PATCH v4 5/6] bus: cdmm: Add MIPS R5 arch support Serge Semin
@ 2020-06-17 22:32 ` Serge Semin
  2020-07-01  7:00   ` Daniel Lezcano
  5 siblings, 1 reply; 11+ messages in thread
From: Serge Semin @ 2020-06-17 22:32 UTC (permalink / raw)
  To: Thomas Gleixner, Rafael J. Wysocki, Daniel Lezcano,
	Thomas Bogendoerfer, Greg Kroah-Hartman
  Cc: Serge Semin, Serge Semin, Marc Zyngier, Alexey Malahov,
	linux-mips, devicetree, linux-kernel

Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
GIC timer and MIPS CPS CPUidle drivers.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Marc Zyngier <maz@kernel.org>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org

---

Changelog v3:
- Keep the files list alphabetically ordered.
- Add Thomas as the co-maintainer of the designated drivers.
---
 MAINTAINERS | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2926327e4976..20532e0287d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11278,6 +11278,17 @@ F:	arch/mips/configs/generic/board-boston.config
 F:	drivers/clk/imgtec/clk-boston.c
 F:	include/dt-bindings/clock/boston-clock.h
 
+MIPS CORE DRIVERS
+M:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+M:	Serge Semin <fancer.lancer@gmail.com>
+L:	linux-mips@vger.kernel.org
+S:	Supported
+F:	drivers/bus/mips_cdmm.c
+F:	drivers/clocksource/mips-gic-timer.c
+F:	drivers/cpuidle/cpuidle-cps.c
+F:	drivers/irqchip/irq-mips-cpu.c
+F:	drivers/irqchip/irq-mips-gic.c
+
 MIPS GENERIC PLATFORM
 M:	Paul Burton <paulburton@kernel.org>
 L:	linux-mips@vger.kernel.org
-- 
2.26.2


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* Re: [PATCH v4 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema
  2020-06-17 22:31 ` [PATCH v4 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
@ 2020-06-29 21:46   ` Rob Herring
  0 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2020-06-29 21:46 UTC (permalink / raw)
  To: Serge Semin
  Cc: devicetree, Serge Semin, Daniel Lezcano, Alexey Malahov,
	Thomas Gleixner, Greg Kroah-Hartman, linux-kernel,
	Thomas Bogendoerfer, linux-mips, Rob Herring, Rafael J. Wysocki,
	Paul Burton

On Thu, 18 Jun 2020 01:31:55 +0300, Serge Semin wrote:
> It's a Cluster Power Controller embedded into the MIPS IP cores.
> Currently the corresponding dts node is supposed to have compatible
> and reg properties.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> 
> ---
> 
> Changelog prev:
> - Reword the changelog summary - use shorter version.
> - Lowercase the example hex'es.
> ---
>  .../bindings/power/mti,mips-cpc.txt           |  8 -----
>  .../bindings/power/mti,mips-cpc.yaml          | 35 +++++++++++++++++++
>  2 files changed, 35 insertions(+), 8 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt
>  create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml
> 


My bot found errors running 'make dt_binding_check' on your patch:

/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/power/mti,mips-cpc.example.dt.yaml: example-0: cpc@1bde0000:reg:0: [0, 467533824, 0, 32768] is too long


See https://patchwork.ozlabs.org/patch/1311661

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:

pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v4 3/6] dt-bindings: bus: Add MIPS CDMM controller
  2020-06-17 22:31 ` [PATCH v4 3/6] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
@ 2020-06-29 21:46   ` Rob Herring
  0 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2020-06-29 21:46 UTC (permalink / raw)
  To: Serge Semin
  Cc: Alexey Malahov, Thomas Bogendoerfer, linux-kernel,
	Thomas Gleixner, devicetree, Daniel Lezcano, linux-mips,
	Rafael J. Wysocki, Serge Semin, Rob Herring, Greg Kroah-Hartman

On Thu, 18 Jun 2020 01:31:57 +0300, Serge Semin wrote:
> It's a Common Device Memory Map controller embedded into the MIPS IP
> cores, which dts node is supposed to have compatible and reg properties.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: linux-mips@vger.kernel.org
> 
> ---
> 
> Changelog prev:
> - Lowercase the example hex'es.
> ---
>  .../bindings/bus/mti,mips-cdmm.yaml           | 35 +++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
> 


My bot found errors running 'make dt_binding_check' on your patch:

/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/bus/mti,mips-cdmm.example.dt.yaml: example-0: cdmm@1bde8000:reg:0: [0, 467566592, 0, 32768] is too long


See https://patchwork.ozlabs.org/patch/1311658

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:

pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade

Please check and re-submit.


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v4 6/6] MAINTAINERS: Add maintainers for MIPS core drivers
  2020-06-17 22:32 ` [PATCH v4 6/6] MAINTAINERS: Add maintainers for MIPS core drivers Serge Semin
@ 2020-07-01  7:00   ` Daniel Lezcano
  2020-07-01 21:28     ` Serge Semin
  0 siblings, 1 reply; 11+ messages in thread
From: Daniel Lezcano @ 2020-07-01  7:00 UTC (permalink / raw)
  To: Serge Semin, Thomas Gleixner, Rafael J. Wysocki,
	Thomas Bogendoerfer, Greg Kroah-Hartman
  Cc: Serge Semin, Marc Zyngier, Alexey Malahov, linux-mips,
	devicetree, linux-kernel

On 18/06/2020 00:32, Serge Semin wrote:
> Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
> GIC timer and MIPS CPS CPUidle drivers.

Why will you add yourself in the MAINTAINERS file for those drivers when
git shows just one contribution for the mips-gic-timer for the timer
stability ?

git shortlog --numbered --summary drivers/cpuidle/cpuidle-cps.c
     4  Paul Burton
     1  Daniel Lezcano
     1  Marcin Nowakowski
     1  Matt Redfearn
     1  Thomas Gleixner

git shortlog --numbered --summary drivers/clocksource/mips-gic-timer.c
    11  Andrew Bresticker
     4  Ezequiel Garcia
     4  Matt Redfearn
     4  Paul Burton
     3  Daniel Lezcano
     3  Thomas Gleixner
     2  Linus Torvalds
     1  Alex Smith
     1  Christophe Jaillet
     1  Felix Fietkau
     1  Ingo Molnar
     1  Markos Chandras
     1  Paul Gortmaker
     1  Rafał Miłecki
     1  Richard Cochran
     1  Serge Semin
     1  Viresh Kumar
     1  YueHaibing

Also, in the cpuidle-cps.c history, there is no signed-off from Rafael,
neither an Acked-by when it was merged. That make me think the patch
went through another path than the linux-pm tree without a cpuidle
framework maintainer acknowledgement.

Perhaps it is a mistake and the patch was actually acked-by, but I would
like to remind the patches have to be acked by the upper maintainers and
being listed in the MAINTAINERS file does not give the right of override
this rule.



> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Acked-by: Marc Zyngier <maz@kernel.org>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> 
> ---
> 
> Changelog v3:
> - Keep the files list alphabetically ordered.
> - Add Thomas as the co-maintainer of the designated drivers.
> ---
>  MAINTAINERS | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 2926327e4976..20532e0287d7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11278,6 +11278,17 @@ F:	arch/mips/configs/generic/board-boston.config
>  F:	drivers/clk/imgtec/clk-boston.c
>  F:	include/dt-bindings/clock/boston-clock.h
>  
> +MIPS CORE DRIVERS
> +M:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> +M:	Serge Semin <fancer.lancer@gmail.com>
> +L:	linux-mips@vger.kernel.org
> +S:	Supported
> +F:	drivers/bus/mips_cdmm.c
> +F:	drivers/clocksource/mips-gic-timer.c
> +F:	drivers/cpuidle/cpuidle-cps.c
> +F:	drivers/irqchip/irq-mips-cpu.c
> +F:	drivers/irqchip/irq-mips-gic.c
> +
>  MIPS GENERIC PLATFORM
>  M:	Paul Burton <paulburton@kernel.org>
>  L:	linux-mips@vger.kernel.org
> 


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH v4 6/6] MAINTAINERS: Add maintainers for MIPS core drivers
  2020-07-01  7:00   ` Daniel Lezcano
@ 2020-07-01 21:28     ` Serge Semin
  0 siblings, 0 replies; 11+ messages in thread
From: Serge Semin @ 2020-07-01 21:28 UTC (permalink / raw)
  To: Daniel Lezcano
  Cc: Thomas Gleixner, Rafael J. Wysocki, Thomas Bogendoerfer,
	Greg Kroah-Hartman, Marc Zyngier, Alexey Malahov, linux-mips,
	devicetree, linux-kernel

Hello Daniel

On Wed, Jul 01, 2020 at 09:00:03AM +0200, Daniel Lezcano wrote:
> On 18/06/2020 00:32, Serge Semin wrote:
> > Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS
> > GIC timer and MIPS CPS CPUidle drivers.
> 

> Why will you add yourself in the MAINTAINERS file for those drivers when
> git shows just one contribution for the mips-gic-timer for the timer
> stability ?
> 
> git shortlog --numbered --summary drivers/cpuidle/cpuidle-cps.c
>      4  Paul Burton
>      1  Daniel Lezcano
>      1  Marcin Nowakowski
>      1  Matt Redfearn
>      1  Thomas Gleixner
> 
> git shortlog --numbered --summary drivers/clocksource/mips-gic-timer.c
>     11  Andrew Bresticker
>      4  Ezequiel Garcia
>      4  Matt Redfearn
>      4  Paul Burton
>      3  Daniel Lezcano
>      3  Thomas Gleixner
>      2  Linus Torvalds
>      1  Alex Smith
>      1  Christophe Jaillet
>      1  Felix Fietkau
>      1  Ingo Molnar
>      1  Markos Chandras
>      1  Paul Gortmaker
>      1  Rafał Miłecki
>      1  Richard Cochran
>      1  Serge Semin
>      1  Viresh Kumar
>      1  YueHaibing

I suppose that the number of commits isn't a main criteria to make someone of
being a maintainer of a particular driver, though it might be a sufficient
condition why someone could be appointed with the role. Anyway as I said in
the cover letter that was a mere suggestion:

> > Suggestion.
> > Since Paul isn't looking after the MIPS arch code anymore, Ralf hasn't
> > been seen maintaining MIPS for a long time, Thomas is only responsible
> > for the next part of it:
> >         F:      Documentation/devicetree/bindings/mips/
> >         F:      Documentation/mips/
> >         F:      arch/mips/
> >         F:      drivers/platform/mips/
> > the MIPS-specific drivers like:
> >         F:      drivers/bus/mips_cdmm.c
> >         F:      drivers/irqchip/irq-mips-cpu.c
> >         F:      drivers/irqchip/irq-mips-gic.c
> >         F:      drivers/clocksource/mips-gic-timer.c
> >         F:      drivers/cpuidle/cpuidle-cps.c
> > seem to be left for the subsystems maintainers to support. So if you don't
> > mind or unless there is a better alternative, I can help with looking
> > after them to ease the maintainers review burden and since I'll be working
> > on our MIPS-based SoC drivers integrating into the mainline kernel repo
> > anyway. Thomas agreed to join in maintaining that drivers."

Primarily I've propose my help with looking after those drivers, since I'll be
working on our SoC drivers with those components installed anyway.

Another reason why I've decided to create this patch is that I've discovered there
is noone looking after the drivers/bus/mips_cdmm.c driver. Noone responded to
accept/decline the CDMM-related changes proposed in this patchset
(mips_cdmm.c driver), noone except Rob responded to the DT bindings conversion
patches (irq-mips-gic.c, mips_cdmm.c drivers):
  68d4fa5d0bb8 dt-bindings: bus: Add MIPS CDMM controller
  7256641fe15e dt-bindings: interrupt-controller: Convert mti,gic to DT schema
  da16cdddd947 dt-bindings: power: Convert mti,mips-cpc to DT schema
Finally I didn't say it in the cover letter, but cpuidle-cps wasn't working for
our SoC, so I'll have to dig into that driver anyway. Moreover It seems to me
that cpuidle-cps.c will be abandoned by the author since Paul Burton stopped
working for MIPS. So based on that I collected all MIPS-related but scattered
around the kernel subsystems drivers (MIPS CDMM, MIPS CPU/GIC IRQ-chip,
MIPS GIC-timer and MIPS CPU-idle CPS) in the dedicated maintainers entry and
proposed my help with their maintenance. By Marc' suggestion Thomas agreed to
join in.

If you don't need our help in maintaining the mips-gic-timer.c and cpuidle-cps.c
drivers, then just say so. I'll discard them from the maintenance entry created
by this patch. Though in that case the list won't be full.)

> 
> Also, in the cpuidle-cps.c history, there is no signed-off from Rafael,
> neither an Acked-by when it was merged. That make me think the patch
> went through another path than the linux-pm tree without a cpuidle
> framework maintainer acknowledgement.
> 
> Perhaps it is a mistake and the patch was actually acked-by, but I would
> like to remind the patches have to be acked by the upper maintainers and
> being listed in the MAINTAINERS file does not give the right of override
> this rule.

Sorry. I don't really get it what patch you are talking about. But I
totally aware of the rule you've mentioned.

-Sergey

> 
> 
> 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Acked-by: Marc Zyngier <maz@kernel.org>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: linux-mips@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > 
> > ---
> > 
> > Changelog v3:
> > - Keep the files list alphabetically ordered.
> > - Add Thomas as the co-maintainer of the designated drivers.
> > ---
> >  MAINTAINERS | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 2926327e4976..20532e0287d7 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -11278,6 +11278,17 @@ F:	arch/mips/configs/generic/board-boston.config
> >  F:	drivers/clk/imgtec/clk-boston.c
> >  F:	include/dt-bindings/clock/boston-clock.h
> >  
> > +MIPS CORE DRIVERS
> > +M:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > +M:	Serge Semin <fancer.lancer@gmail.com>
> > +L:	linux-mips@vger.kernel.org
> > +S:	Supported
> > +F:	drivers/bus/mips_cdmm.c
> > +F:	drivers/clocksource/mips-gic-timer.c
> > +F:	drivers/cpuidle/cpuidle-cps.c
> > +F:	drivers/irqchip/irq-mips-cpu.c
> > +F:	drivers/irqchip/irq-mips-gic.c
> > +
> >  MIPS GENERIC PLATFORM
> >  M:	Paul Burton <paulburton@kernel.org>
> >  L:	linux-mips@vger.kernel.org
> > 
> 
> 
> -- 
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
> 
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog

^ permalink raw reply	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2020-07-01 21:28 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-17 22:31 [PATCH RESEND v4 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
2020-06-17 22:31 ` [PATCH v4 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
2020-06-29 21:46   ` Rob Herring
2020-06-17 22:31 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Convert mti,gic " Serge Semin
2020-06-17 22:31 ` [PATCH v4 3/6] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
2020-06-29 21:46   ` Rob Herring
2020-06-17 22:31 ` [PATCH v4 4/6] mips: cdmm: Add mti,mips-cdmm dtb node support Serge Semin
2020-06-17 22:31 ` [PATCH v4 5/6] bus: cdmm: Add MIPS R5 arch support Serge Semin
2020-06-17 22:32 ` [PATCH v4 6/6] MAINTAINERS: Add maintainers for MIPS core drivers Serge Semin
2020-07-01  7:00   ` Daniel Lezcano
2020-07-01 21:28     ` Serge Semin

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