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* [PATCH] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
@ 2020-02-06 19:30 Kamal Dasu
  2020-02-07  3:55 ` Florian Fainelli
  0 siblings, 1 reply; 2+ messages in thread
From: Kamal Dasu @ 2020-02-06 19:30 UTC (permalink / raw)
  To: linux-kernel
  Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
	Rob Herring, Mark Rutland, Florian Fainelli, Ralf Baechle,
	Paul Burton, James Hogan, Brian Norris, Sumit Semwal, linux-mtd,
	devicetree, bcm-kernel-feedback-list, linux-mips, linux-media,
	dri-devel, linaro-mm-sig

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
line can contain two instruction cache lines (64B), or four data cache
lines (32B). Hardware prefetch Cache detects stream access, and prefetches
ahead of processor access. Add support to inavalidate BMIPS5000 cpu zephyr
secondary cache module (ZSCM) on DMA from device so that data returned is
coherent during DMA read operations.

Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
 arch/mips/mm/c-r4k.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5f3d0103b95d..2d8892ba68ab 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -901,6 +901,35 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 	__sync();
 }
 
+static void prefetch_cache_inv(unsigned long addr, unsigned long size)
+{
+	unsigned int linesz = cpu_scache_line_size();
+	unsigned long addr0 = addr, addr1;
+	int cpu_type = current_cpu_type();
+
+	if (cpu_type == CPU_BMIPS5000) {
+		/* invalidate zephyr secondary cache module prefetch lines */
+		addr0 &= ~(linesz - 1);
+		addr1 = (addr0 + size - 1) & ~(linesz - 1);
+
+		protected_writeback_scache_line(addr0);
+		if (likely(addr1 != addr0))
+			protected_writeback_scache_line(addr1);
+		else
+			return;
+
+		addr0 += linesz;
+		if (likely(addr1 != addr0))
+			protected_writeback_scache_line(addr0);
+		else
+			return;
+
+		addr1 -= linesz;
+		if (likely(addr1 > addr0))
+			protected_writeback_scache_line(addr0);
+	}
+}
+
 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 {
 	/* Catch bad driver code */
@@ -908,6 +937,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 		return;
 
 	preempt_disable();
+	prefetch_cache_inv(addr, size);
 	if (cpu_has_inclusive_pcaches) {
 		if (size >= scache_size) {
 			if (current_cpu_type() != CPU_LOONGSON64)
-- 
2.17.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
  2020-02-06 19:30 [PATCH] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines Kamal Dasu
@ 2020-02-07  3:55 ` Florian Fainelli
  0 siblings, 0 replies; 2+ messages in thread
From: Florian Fainelli @ 2020-02-07  3:55 UTC (permalink / raw)
  To: Kamal Dasu, linux-kernel
  Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
	Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
	James Hogan, Brian Norris, Sumit Semwal, linux-mtd, devicetree,
	bcm-kernel-feedback-list, linux-mips, linux-media, dri-devel,
	linaro-mm-sig



On 2/6/2020 11:30 AM, Kamal Dasu wrote:
> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> line can contain two instruction cache lines (64B), or four data cache
> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> ahead of processor access. Add support to inavalidate BMIPS5000 cpu zephyr

s/inavalidate/invalidate/

> secondary cache module (ZSCM) on DMA from device so that data returned is
> coherent during DMA read operations.

Just a few nits, see below, with those addressed:

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>

> 
> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
> ---
>  arch/mips/mm/c-r4k.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 5f3d0103b95d..2d8892ba68ab 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -901,6 +901,35 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
>  	__sync();
>  }
>  
> +static void prefetch_cache_inv(unsigned long addr, unsigned long size)
> +{
> +	unsigned int linesz = cpu_scache_line_size();
> +	unsigned long addr0 = addr, addr1;
> +	int cpu_type = current_cpu_type();
> +
> +	if (cpu_type == CPU_BMIPS5000) {

I would re-organize this and move this out of the prefetch_cache_inv()
such that platforms which do not require that operation can have it
optimized out, see below:

> +		/* invalidate zephyr secondary cache module prefetch lines */
> +		addr0 &= ~(linesz - 1);
> +		addr1 = (addr0 + size - 1) & ~(linesz - 1);
> +
> +		protected_writeback_scache_line(addr0);
> +		if (likely(addr1 != addr0))
> +			protected_writeback_scache_line(addr1);
> +		else
> +			return;
> +
> +		addr0 += linesz;
> +		if (likely(addr1 != addr0))
> +			protected_writeback_scache_line(addr0);
> +		else
> +			return;
> +
> +		addr1 -= linesz;
> +		if (likely(addr1 > addr0))
> +			protected_writeback_scache_line(addr0);
> +	}
> +}
> +
>  static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
>  {
>  	/* Catch bad driver code */
> @@ -908,6 +937,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
>  		return;
>  
>  	preempt_disable();

	if (current_cpu_type() == CPU_BMIPS5000)
		prefetch_cache_inv(addr, size);

> +	prefetch_cache_inv(addr, size);
>  	if (cpu_has_inclusive_pcaches) {
>  		if (size >= scache_size) {
>  			if (current_cpu_type() != CPU_LOONGSON64)
> 

-- 
Florian

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2020-02-06 19:30 [PATCH] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines Kamal Dasu
2020-02-07  3:55 ` Florian Fainelli

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