From: Ben Hutchings <ben@decadent.org.uk>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: akpm@linux-foundation.org, "James Hogan" <james.hogan@imgtec.com>,
"Ralf Baechle" <ralf@linux-mips.org>,
linux-mips@linux-mips.org, "Paul Burton" <paul.burton@imgtec.com>
Subject: [PATCH 3.16 22/26] MIPS: traps: Fix inline asm ctc1 missing .set hardfloat
Date: Sun, 02 Apr 2017 04:04:24 +0100 [thread overview]
Message-ID: <lsq.1491102264.593686941@decadent.org.uk> (raw)
In-Reply-To: <lsq.1491102264.9835075@decadent.org.uk>
3.16.43-rc2 review patch. If anyone has any objections, please let me know.
------------------
From: James Hogan <james.hogan@imgtec.com>
commit d76e9b9fc5de7e8fc4fd0e72a94e8c723929ffea upstream.
Commit 842dfc11ea9a ("MIPS: Fix build with binutils 2.24.51+") in v3.18
enabled -msoft-float and sprinkled ".set hardfloat" where necessary to
use FP instructions. However it missed enable_restore_fp_context() which
since v3.17 does a ctc1 with inline assembly, causing the following
assembler errors on Mentor's 2014.05 toolchain:
{standard input}: Assembler messages:
{standard input}:2913: Error: opcode not supported on this processor: mips32r2 (mips32r2) `ctc1 $2,$31'
scripts/Makefile.build:257: recipe for target 'arch/mips/kernel/traps.o' failed
Fix that to use the new write_32bit_cp1_register() macro so that ".set
hardfloat" is automatically added when -msoft-float is in use.
Fixes 842dfc11ea9a ("MIPS: Fix build with binutils 2.24.51+")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9173/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
arch/mips/kernel/traps.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1183,7 +1183,8 @@ static int enable_restore_fp_context(int
/* Restore the scalar FP control & status register */
if (!was_fpu_owner)
- asm volatile("ctc1 %0, $31" : : "r"(current->thread.fpu.fcr31));
+ write_32bit_cp1_register(CP1_STATUS,
+ current->thread.fpu.fcr31);
}
return 0;
}
next prev parent reply other threads:[~2017-04-02 3:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <lsq.1491102264.9835075@decadent.org.uk>
2017-04-02 3:04 ` [PATCH 3.16 26/26] MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support Ben Hutchings
2017-04-02 3:04 ` [PATCH 3.16 20/26] MIPS: allow msa.h to be included in assembly files Ben Hutchings
2017-04-02 3:04 ` Ben Hutchings [this message]
2017-04-02 3:04 ` [PATCH 3.16 21/26] MIPS: mipsregs.h: Add write_32bit_cp1_register() Ben Hutchings
2017-04-02 3:04 ` [PATCH 3.16 25/26] MIPS: remove MSA macro recursion Ben Hutchings
2017-04-02 3:04 ` [PATCH 3.16 23/26] MIPS: Push .set mips64r* into the functions needing it Ben Hutchings
2017-04-02 3:04 ` [PATCH 3.16 24/26] MIPS: assume at as source/dest of MSA copy/insert instructions Ben Hutchings
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