From: Ingo Molnar <mingo@kernel.org>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
Linus Torvalds <torvalds@linux-foundation.org>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Andrew Morton <akpm@linux-foundation.org>,
Andy Lutomirski <luto@amacapital.net>,
Cyrill Gorcunov <gorcunov@openvz.org>,
Borislav Petkov <bp@suse.de>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCHv7 06/19] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time
Date: Thu, 28 Sep 2017 10:18:25 +0200 [thread overview]
Message-ID: <20170928081825.mq3gccldrgbvjlnc@gmail.com> (raw)
In-Reply-To: <20170918105553.27914-7-kirill.shutemov@linux.intel.com>
* Kirill A. Shutemov <kirill.shutemov@linux.intel.com> wrote:
> This patch prepare decompression code to boot-time switching between 4-
> and 5-level paging.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> ---
> arch/x86/boot/compressed/head_64.S | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
> index b4a5d284391c..09c85e8558eb 100644
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -288,6 +288,28 @@ ENTRY(startup_64)
> leaq boot_stack_end(%rbx), %rsp
>
> #ifdef CONFIG_X86_5LEVEL
> + /* Preserve rbx across cpuid */
> + movq %rbx, %r8
> +
> + /* Check if leaf 7 is supported */
> + xorl %eax, %eax
> + cpuid
> + cmpl $7, %eax
> + jb lvl5
> +
> + /*
> + * Check if la57 is supported.
> + * The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]
> + */
> + movl $7, %eax
> + xorl %ecx, %ecx
> + cpuid
> + andl $(1 << 16), %ecx
> + jz lvl5
> +
> + /* Restore rbx */
In (new) x86 asm code we refer to registers in capital letters.
Also, CPUID should be capitalized consistently as well.
Also, LA57 should be capitalized as well.
> + movq %r8, %rbx
> +
> /* Check if 5-level paging has already enabled */
> movq %cr4, %rax
BTW., please also fix the typo in this comment while at it.
Thanks,
Ingo
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next prev parent reply other threads:[~2017-09-28 8:18 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-18 10:55 [PATCHv7 00/19] Boot-time switching between 4- and 5-level paging for 4.15 Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 01/19] mm/sparsemem: Allocate mem_section at runtime for SPARSEMEM_EXTREME Kirill A. Shutemov
2017-09-28 8:07 ` Ingo Molnar
2017-09-28 9:08 ` Kirill A. Shutemov
2017-09-28 9:39 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 02/19] mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS Kirill A. Shutemov
2017-09-28 8:10 ` Ingo Molnar
2017-09-28 9:19 ` Kirill A. Shutemov
2017-09-28 9:44 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 03/19] x86/kasan: Use the same shadow offset for 4- and 5-level paging Kirill A. Shutemov
2017-09-28 8:15 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 04/19] x86/xen: Provide pre-built page tables only for XEN_PV and XEN_PVH Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 05/19] x86/xen: Drop 5-level paging support code from XEN_PV code Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 06/19] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Kirill A. Shutemov
2017-09-28 8:18 ` Ingo Molnar [this message]
2017-09-18 10:55 ` [PATCHv7 07/19] x86/mm: Make virtual memory layout movable for CONFIG_X86_5LEVEL Kirill A. Shutemov
2017-09-28 8:19 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 08/19] x86/mm: Make PGDIR_SHIFT and PTRS_PER_P4D variable Kirill A. Shutemov
2017-09-19 14:03 ` Kirill A. Shutemov
2017-09-28 8:21 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 09/19] x86/mm: Make MAX_PHYSADDR_BITS and MAX_PHYSMEM_BITS dynamic Kirill A. Shutemov
2017-09-28 8:25 ` Ingo Molnar
2017-09-28 10:17 ` Kirill A. Shutemov
2017-09-28 10:40 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 10/19] x86/mm: Make __PHYSICAL_MASK_SHIFT and __VIRTUAL_MASK_SHIFT dynamic Kirill A. Shutemov
2017-09-28 8:28 ` Ingo Molnar
2017-09-28 10:22 ` Kirill A. Shutemov
2017-09-28 10:42 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 11/19] x86/mm: Make STACK_TOP_MAX dynamic Kirill A. Shutemov
2017-09-28 8:29 ` Ingo Molnar
2017-09-28 13:19 ` Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 12/19] x86/mm: Adjust virtual address space layout in early boot Kirill A. Shutemov
2017-09-28 8:31 ` Ingo Molnar
2017-09-28 13:26 ` Kirill A. Shutemov
2017-09-28 13:38 ` Ingo Molnar
2017-09-28 14:28 ` Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 13/19] x86/mm: Make early boot code support boot-time switching of paging modes Kirill A. Shutemov
2017-09-28 8:33 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 14/19] x86/mm: Fold p4d page table layer at runtime Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 15/19] x86/mm: Replace compile-time checks for 5-level with runtime-time Kirill A. Shutemov
2017-09-28 8:35 ` Ingo Molnar
2017-09-18 10:55 ` [PATCHv7 16/19] x86/mm: Allow to boot without la57 if CONFIG_X86_5LEVEL=y Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 17/19] x86/xen: Allow XEN_PV and XEN_PVH to be enabled with X86_5LEVEL Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 18/19] x86/mm: Redefine some of page table helpers as macros Kirill A. Shutemov
2017-09-18 10:55 ` [PATCHv7 19/19] x86/mm: Offset boot-time paging mode switching cost Kirill A. Shutemov
2017-09-25 13:16 ` [PATCHv7 00/19] Boot-time switching between 4- and 5-level paging for 4.15 Kirill A. Shutemov
2017-09-28 8:36 ` Ingo Molnar
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