From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-f69.google.com (mail-oi0-f69.google.com [209.85.218.69]) by kanga.kvack.org (Postfix) with ESMTP id BF92B6B0253 for ; Tue, 21 Nov 2017 07:29:48 -0500 (EST) Received: by mail-oi0-f69.google.com with SMTP id w205so5944931oig.7 for ; Tue, 21 Nov 2017 04:29:48 -0800 (PST) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com. [217.140.101.70]) by mx.google.com with ESMTP id u5si5084486oif.132.2017.11.21.04.29.47 for ; Tue, 21 Nov 2017 04:29:47 -0800 (PST) Date: Tue, 21 Nov 2017 12:29:38 +0000 From: Mark Rutland Subject: Re: =?utf-8?B?562U5aSN?= =?utf-8?Q?=3A?= [PATCH 01/11] Initialize the mapping of KASan shadow memory Message-ID: <20171121122938.sydii3i36jbzi7x4@lakrids.cambridge.arm.com> References: <87po8ir1kg.fsf@on-the-bus.cambridge.arm.com> <87375eqobb.fsf@on-the-bus.cambridge.arm.com> <20171117073556.GB28855@cbox> <20171118134841.3f6c9183@why.wild-wind.fr.eu.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: owner-linux-mm@kvack.org List-ID: To: "Liuwenliang (Abbott Liu)" Cc: Marc Zyngier , "tixy@linaro.org" , "mhocko@suse.com" , "grygorii.strashko@linaro.org" , "catalin.marinas@arm.com" , "linux-mm@kvack.org" , "glider@google.com" , "afzal.mohd.ma@gmail.com" , "mingo@kernel.org" , Christoffer Dall , "f.fainelli@gmail.com" , "mawilcox@microsoft.com" , "linux@armlinux.org.uk" , "kasan-dev@googlegroups.com" , Dailei , "linux-arm-kernel@lists.infradead.org" , "aryabinin@virtuozzo.com" , "labbott@redhat.com" , "vladimir.murzin@arm.com" , "keescook@chromium.org" , "arnd@arndb.de" , Zengweilin , "opendmb@gmail.com" , Heshaoliang , "tglx@linutronix.de" , "dvyukov@google.com" , "ard.biesheuvel@linaro.org" , "linux-kernel@vger.kernel.org" , Jiazhenghua , "akpm@linux-foundation.org" , "robin.murphy@arm.com" , "thgarnie@google.com" , "kirill.shutemov@linux.intel.com" On Tue, Nov 21, 2017 at 07:59:01AM +0000, Liuwenliang (Abbott Liu) wrote: > On Nov 17, 2017 21:49 Marc Zyngier [mailto:marc.zyngier@arm.com] wrote: > >On Sat, 18 Nov 2017 10:40:08 +0000 > >"Liuwenliang (Abbott Liu)" wrote: > >> On Nov 17, 2017 15:36 Christoffer Dall [mailto:cdall@linaro.org] wrote: > Please don't ask people to limit to 4GB of physical space on CPU > supporting LPAE, please don't ask people to guaranteed to have some > memory below 4GB on CPU supporting LPAE. I don't think that Marc is suggesting that you'd always use the 32-bit accessors on an LPAE system, just that all the definitions should exist regardless of configuration. So rather than this: > +#ifdef CONFIG_ARM_LPAE > +#define TTBR0 __ACCESS_CP15_64(0, c2) > +#define TTBR1 __ACCESS_CP15_64(1, c2) > +#define PAR __ACCESS_CP15_64(0, c7) > +#else > +#define TTBR0 __ACCESS_CP15(c2, 0, c0, 0) > +#define TTBR1 __ACCESS_CP15(c2, 0, c0, 1) > +#define PAR __ACCESS_CP15(c7, 0, c4, 0) > +#endif ... you'd have the following in cp15.h: #define TTBR0_64 __ACCESS_CP15_64(0, c2) #define TTBR1_64 __ACCESS_CP15_64(1, c2) #define PAR_64 __ACCESS_CP15_64(0, c7) #define TTBR0_32 __ACCESS_CP15(c2, 0, c0, 0) #define TTBR1_32 __ACCESS_CP15(c2, 0, c0, 1) #define PAR_32 __ACCESS_CP15(c7, 0, c4, 0) ... and elsewhere, where it matters, we choose which to use depending on the kernel configuration, e.g. void set_ttbr0(u64 val) { if (IS_ENABLED(CONFIG_ARM_LPAE)) write_sysreg(val, TTBR0_64); else write_sysreg(val, TTBR0_32); } Thanks, Mark. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org