From: Baoquan He <bhe@redhat.com>
To: "Kirill A. Shutemov" <kirill@shutemov.name>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, dave.hansen@linux.intel.com, luto@kernel.org,
peterz@infradead.org, boris.ostrovsky@oracle.com,
jgross@suse.com, willy@infradead.org, x86@kernel.org,
linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCHv2 1/2] x86/mm: Move LDT remap out of KASLR region on 5-level paging
Date: Thu, 25 Oct 2018 16:11:00 +0800 [thread overview]
Message-ID: <20181025081100.GA31346@MiWiFi-R3L-srv> (raw)
In-Reply-To: <20181025072429.k54aem37sefqonqy@kshutemo-mobl1>
On 10/25/18 at 10:24am, Kirill A. Shutemov wrote:
> On Thu, Oct 25, 2018 at 10:18:09AM +0800, Baoquan He wrote:
> > > We don't touch 4 pgd slot gap just before the direct mapping reserved
> > > for a hypervisor, but move direct mapping by one slot instead.
> > >
> > > The LDT mapping is per-mm, so we cannot move it into P4D page table next
> > > to CPU_ENTRY_AREA without complicating PGD table allocation for 5-level
> > > paging.
> >
> > Here as discussed in private thread, at the first place you also agreed
> > to put it in p4d entry next to CPU_ENTRY_AREA, but finally you changd
> > mind, there must be some reasons when you implemented and investigated
> > further to find out. Could you please say more about how it will
> > complicating PGD table allocation for 5-level paging? Or give an use
> > case where it will complicate?
>
> On 5-level machine all memory starting from CPU_ENTRY_AREA (and part of
> KASAN memory) is in the same P4D page table. All this memory is shared
> across all processes, we just copy PGD entry -- all proceses point to the
> same P4D page table. (I leave out PTI from the picture for simplicity.)
Yes, got it, I didn't notice this, thanks a lot.
next prev parent reply other threads:[~2018-10-25 8:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 12:51 [PATCHv2 0/2] Fix couple of issues with LDT remap for PTI Kirill A. Shutemov
2018-10-24 12:51 ` [PATCHv2 1/2] x86/mm: Move LDT remap out of KASLR region on 5-level paging Kirill A. Shutemov
2018-10-24 13:12 ` Matthew Wilcox
2018-10-25 2:18 ` Baoquan He
2018-10-25 7:24 ` Kirill A. Shutemov
2018-10-25 8:11 ` Baoquan He [this message]
2018-10-24 12:51 ` [PATCHv2 2/2] x86/ldt: Unmap PTEs for the slot before freeing LDT pages Kirill A. Shutemov
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