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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 3 Dec 2019 03:48:18 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xB33mHb640894600 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 3 Dec 2019 03:48:17 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AF9F14C04A; Tue, 3 Dec 2019 03:48:17 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 14F4D4C04E; Tue, 3 Dec 2019 03:48:17 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 3 Dec 2019 03:48:17 +0000 (GMT) Received: from adsilva.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 02A3AA03DE; Tue, 3 Dec 2019 14:48:13 +1100 (AEDT) From: "Alastair D'Silva" To: alastair@d-silva.org Cc: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Frederic Barrat , Andrew Donnellan , Arnd Bergmann , Greg Kroah-Hartman , Dan Williams , Vishal Verma , Dave Jiang , Keith Busch , Ira Weiny , Andrew Morton , Mauro Carvalho Chehab , "David S. Miller" , Rob Herring , Anton Blanchard , Krzysztof Kozlowski , Mahesh Salgaonkar , Madhavan Srinivasan , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Anju T Sudhakar , Hari Bathini , Thomas Gleixner , Greg Kurz , Nicholas Piggin , Masahiro Yamada , Alexey Kardashevskiy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-nvdimm@lists.01.org, linux-mm@kvack.org Subject: [PATCH v2 12/27] nvdimm/ocxl: Read the capability registers & wait for device ready Date: Tue, 3 Dec 2019 14:46:40 +1100 X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191203034655.51561-1-alastair@au1.ibm.com> References: <20191203034655.51561-1-alastair@au1.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19120303-0008-0000-0000-0000033C0FDD X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19120303-0009-0000-0000-00004A5B289B Message-Id: <20191203034655.51561-13-alastair@au1.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-02_06:2019-11-29,2019-12-02 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 spamscore=0 phishscore=0 suspectscore=1 adultscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912030032 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Alastair D'Silva This patch reads timeouts & firmware version from the controller, and uses those timeouts to wait for the controller to report that it is ready before handing the memory over to libnvdimm. Signed-off-by: Alastair D'Silva --- drivers/nvdimm/ocxl/Makefile | 2 +- drivers/nvdimm/ocxl/scm.c | 84 ++++++++++++++++++++++++++++++ drivers/nvdimm/ocxl/scm_internal.c | 19 +++++++ drivers/nvdimm/ocxl/scm_internal.h | 24 +++++++++ 4 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 drivers/nvdimm/ocxl/scm_internal.c diff --git a/drivers/nvdimm/ocxl/Makefile b/drivers/nvdimm/ocxl/Makefile index 74a1bd98848e..9b6e31f0eb3e 100644 --- a/drivers/nvdimm/ocxl/Makefile +++ b/drivers/nvdimm/ocxl/Makefile @@ -4,4 +4,4 @@ ccflags-$(CONFIG_PPC_WERROR) +=3D -Werror =20 obj-$(CONFIG_OCXL_SCM) +=3D ocxlscm.o =20 -ocxlscm-y :=3D scm.o +ocxlscm-y :=3D scm.o scm_internal.o diff --git a/drivers/nvdimm/ocxl/scm.c b/drivers/nvdimm/ocxl/scm.c index 571058a9e7b8..8088f65c289e 100644 --- a/drivers/nvdimm/ocxl/scm.c +++ b/drivers/nvdimm/ocxl/scm.c @@ -7,6 +7,7 @@ =20 #include #include +#include #include #include #include @@ -266,6 +267,30 @@ static int scm_register_lpc_mem(struct scm_data *scm= _data) return 0; } =20 +/** + * scm_is_usable() - Is a controller usable? + * @scm_data: a pointer to the SCM device data + * Return: true if the controller is usable + */ +static bool scm_is_usable(const struct scm_data *scm_data) +{ + u64 chi =3D 0; + int rc =3D scm_chi(scm_data, &chi); + + if (!(chi & GLOBAL_MMIO_CHI_CRDY)) { + dev_err(&scm_data->dev, "SCM controller is not ready.\n"); + return false; + } + + if (!(chi & GLOBAL_MMIO_CHI_MA)) { + dev_err(&scm_data->dev, + "SCM controller does not have memory available.\n"); + return false; + } + + return true; +} + /** * allocate_scm_minor() - Allocate a minor number to use for an SCM devi= ce * @scm_data: The SCM device to associate the minor with @@ -380,6 +405,48 @@ static void scm_remove(struct pci_dev *pdev) } } =20 +/** + * read_device_metadata() - Retrieve config information from the AFU and= save it for future use + * @scm_data: the SCM metadata + * Return: 0 on success, negative on failure + */ +static int read_device_metadata(struct scm_data *scm_data) +{ + u64 val; + int rc; + + rc =3D ocxl_global_mmio_read64(scm_data->ocxl_afu, GLOBAL_MMIO_CCAP0, + OCXL_LITTLE_ENDIAN, &val); + if (rc) + return rc; + + scm_data->scm_revision =3D val & 0xFFFF; + scm_data->read_latency =3D (val >> 32) & 0xFF; + scm_data->readiness_timeout =3D (val >> 48) & 0xff; + scm_data->memory_available_timeout =3D val >> 52; + + rc =3D ocxl_global_mmio_read64(scm_data->ocxl_afu, GLOBAL_MMIO_CCAP1, + OCXL_LITTLE_ENDIAN, &val); + if (rc) + return rc; + + scm_data->max_controller_dump_size =3D val & 0xFFFFFFFF; + + // Extract firmware version text + rc =3D ocxl_global_mmio_read64(scm_data->ocxl_afu, GLOBAL_MMIO_FWVER, + OCXL_HOST_ENDIAN, (u64 *)scm_data->fw_version); + if (rc) + return rc; + + scm_data->fw_version[8] =3D '\0'; + + dev_info(&scm_data->dev, + "Firmware version '%s' SCM revision %d:%d\n", scm_data->fw_version, + scm_data->scm_revision >> 4, scm_data->scm_revision & 0x0F); + + return 0; +} + /** * scm_probe_function_0 - Set up function 0 for an OpenCAPI Storage Clas= s Memory device * This is important as it enables templates higher than 0 across all ot= her functions, @@ -420,6 +487,8 @@ static int scm_probe_function_0(struct pci_dev *pdev) static int scm_probe(struct pci_dev *pdev, const struct pci_device_id *e= nt) { struct scm_data *scm_data =3D NULL; + int elapsed; + u16 timeout; =20 if (PCI_FUNC(pdev->devfn) =3D=3D 0) return scm_probe_function_0(pdev); @@ -469,6 +538,21 @@ static int scm_probe(struct pci_dev *pdev, const str= uct pci_device_id *ent) goto err; } =20 + if (read_device_metadata(scm_data)) { + dev_err(&pdev->dev, "Could not read SCM device metadata\n"); + goto err; + } + + elapsed =3D 0; + timeout =3D scm_data->readiness_timeout + scm_data->memory_available_ti= meout; + while (!scm_is_usable(scm_data)) { + if (elapsed++ > timeout) { + dev_warn(&scm_data->dev, "SCM ready timeout.\n"); + goto err; + } + + msleep(1000); + } if (scm_register_lpc_mem(scm_data)) { dev_err(&pdev->dev, "Could not register OCXL SCM memory with libnvdimm= \n"); goto err; diff --git a/drivers/nvdimm/ocxl/scm_internal.c b/drivers/nvdimm/ocxl/scm= _internal.c new file mode 100644 index 000000000000..72d3c0e7d846 --- /dev/null +++ b/drivers/nvdimm/ocxl/scm_internal.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 IBM Corp. + +#include +#include +#include "scm_internal.h" + +int scm_chi(const struct scm_data *scm_data, u64 *chi) +{ + u64 val; + int rc =3D ocxl_global_mmio_read64(scm_data->ocxl_afu, GLOBAL_MMIO_CHI, + OCXL_LITTLE_ENDIAN, &val); + if (rc) + return rc; + + *chi =3D val; + + return 0; +} diff --git a/drivers/nvdimm/ocxl/scm_internal.h b/drivers/nvdimm/ocxl/scm= _internal.h index d6ab361f5de9..584450f55e30 100644 --- a/drivers/nvdimm/ocxl/scm_internal.h +++ b/drivers/nvdimm/ocxl/scm_internal.h @@ -97,4 +97,28 @@ struct scm_data { void *metadata_addr; struct resource scm_res; struct nd_region *nd_region; + char fw_version[8+1]; + + u32 max_controller_dump_size; + u16 scm_revision; // major/minor + u8 readiness_timeout; /* The worst case time (in seconds) that the hos= t shall + * wait for the controller to become operational following a reset (C= HI.CRDY). + */ + u8 memory_available_timeout; /* The worst case time (in seconds) that= the host shall + * wait for memory to become available following a reset (CHI.MA). + */ + + u16 read_latency; /* The nominal measure of latency (in nanoseconds) + * associated with an unassisted read of a memory block. + * This represents the capability of the raw media technology witho= ut assistance + */ }; + +/** + * scm_chi() - Get the value of the CHI register + * @scm_data: The SCM metadata + * @chi: returns the CHI value + * + * Returns 0 on success, negative on error + */ +int scm_chi(const struct scm_data *scm_data, u64 *chi); --=20 2.23.0