From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACB74C3F2D8 for ; Wed, 4 Mar 2020 14:10:55 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 71E1E2166E for ; Wed, 4 Mar 2020 14:10:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Q/6/YBab" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 71E1E2166E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 050C26B0005; Wed, 4 Mar 2020 09:10:55 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 0037F6B0006; Wed, 4 Mar 2020 09:10:54 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id DE4046B0007; Wed, 4 Mar 2020 09:10:54 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0213.hostedemail.com [216.40.44.213]) by kanga.kvack.org (Postfix) with ESMTP id C7AD96B0005 for ; Wed, 4 Mar 2020 09:10:54 -0500 (EST) Received: from smtpin09.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id 73B9D181AEF09 for ; Wed, 4 Mar 2020 14:10:54 +0000 (UTC) X-FDA: 76557866028.09.glass24_7e2b5acf7e17 X-HE-Tag: glass24_7e2b5acf7e17 X-Filterd-Recvd-Size: 5487 Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by imf30.hostedemail.com (Postfix) with ESMTP for ; Wed, 4 Mar 2020 14:10:54 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id j7so2540607wrp.13 for ; Wed, 04 Mar 2020 06:10:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=7HwHHOirHwI1c4j5Tv3u9lHj4prOjYmBbBNbHrFitZg=; b=Q/6/YBabh+3hoAX2lwxr9pv+BA6F8RdNG6tLtX1bg/aislj9n8Gmj4CeXizdPlqgft CmQpjJEBAbscYl1+fBWSTwIw3Q+wl4TrDmjZJrl5wmkDlW6cEO2OLALqUjnUpgfw44/u XRD2SH+U+3LGbzsauCnxCczIwaG31q4mtJq6cN5NZdMgXdtdPJRXNnmjCr+94tPg+lLA KHTfh6h5pCiaaBcIZl39MWPMll42zzUvIORJenCDE9jzUv9vXF8eUanvdU7aIzACWArf 8xEZxTj5/LYzGeCYId9/Id5fwR1H6KylI5CO0NUUG2UMvrQ0U4LwsnJmTGCM23qHOhp1 tgUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=7HwHHOirHwI1c4j5Tv3u9lHj4prOjYmBbBNbHrFitZg=; b=RY8oMS/60Js2b/QeWkUWT6b3zFqmj27AUaaJDUEbuezW8dmN3YJcQT2XU2tb1za+2U CvChGgOI/Tluz8XFGoh1jsW5p4Kh9864GvkXbOT6JBB7b70InXdgQVsEZtr7H5F9V45m 9zNb5Mo552MBtI2MDg+0HcWvEjYc9cbUHom5J9wcRSgWVW/Rd9fHEfl3MU5bDOKipVyi 9XBuTg24Y9JymiBI8mcZDg3m1MFYsk1xkMD2GIKzcxVbQz3r+CVnJpNxmQSs+/2QOcLs 32JhDTtMuV86PEeRlwG3NwthetQs59i9/DjUZGsiEUmDt/xVTrgfKDLwccSqALqw/AnU ka1w== X-Gm-Message-State: ANhLgQ0r6ZE7QxvSJXTv2eg3EnnT6z6+XWDCYnsOKuMqXWCs89lW6/BV 9/f3lUA/N4J2LzoCBOt1QUdeHg== X-Google-Smtp-Source: ADFU+vtjRZ/ieGhvG1dNL4yvCidxtjrzWvostamf6vAXdMbRNS014Ivp7HqYWw4uSzXl8u6GytSgWA== X-Received: by 2002:a5d:698a:: with SMTP id g10mr4347543wru.155.1583331052514; Wed, 04 Mar 2020 06:10:52 -0800 (PST) Received: from myrica ([2001:171b:c9a8:fbc0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id t124sm4805947wmg.13.2020.03.04.06.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 06:10:52 -0800 (PST) Date: Wed, 4 Mar 2020 15:10:45 +0100 From: Jean-Philippe Brucker To: Jonathan Cameron Cc: iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-mm@kvack.org, joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, kevin.tian@intel.com, baolu.lu@linux.intel.com, jacob.jun.pan@linux.intel.com, christian.koenig@amd.com, yi.l.liu@intel.com, zhangfei.gao@linaro.org, Jean-Philippe Brucker Subject: Re: [PATCH v4 07/26] arm64: mm: Pin down ASIDs for sharing mm with devices Message-ID: <20200304141045.GD646000@myrica> References: <20200224182401.353359-1-jean-philippe@linaro.org> <20200224182401.353359-8-jean-philippe@linaro.org> <20200227174351.00004d0d@Huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200227174351.00004d0d@Huawei.com> X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Thu, Feb 27, 2020 at 05:43:51PM +0000, Jonathan Cameron wrote: > On Mon, 24 Feb 2020 19:23:42 +0100 > Jean-Philippe Brucker wrote: > > > From: Jean-Philippe Brucker > > > > To enable address space sharing with the IOMMU, introduce mm_context_get() > > and mm_context_put(), that pin down a context and ensure that it will keep > > its ASID after a rollover. Export the symbols to let the modular SMMUv3 > > driver use them. > > > > Pinning is necessary because a device constantly needs a valid ASID, > > unlike tasks that only require one when running. Without pinning, we would > > need to notify the IOMMU when we're about to use a new ASID for a task, > > and it would get complicated when a new task is assigned a shared ASID. > > Consider the following scenario with no ASID pinned: > > > > 1. Task t1 is running on CPUx with shared ASID (gen=1, asid=1) > > 2. Task t2 is scheduled on CPUx, gets ASID (1, 2) > > 3. Task tn is scheduled on CPUy, a rollover occurs, tn gets ASID (2, 1) > > We would now have to immediately generate a new ASID for t1, notify > > the IOMMU, and finally enable task tn. We are holding the lock during > > all that time, since we can't afford having another CPU trigger a > > rollover. The IOMMU issues invalidation commands that can take tens of > > milliseconds. > > > > It gets needlessly complicated. All we wanted to do was schedule task tn, > > that has no business with the IOMMU. By letting the IOMMU pin tasks when > > needed, we avoid stalling the slow path, and let the pinning fail when > > we're out of shareable ASIDs. > > > > After a rollover, the allocator expects at least one ASID to be available > > in addition to the reserved ones (one per CPU). So (NR_ASIDS - NR_CPUS - > > 1) is the maximum number of ASIDs that can be shared with the IOMMU. > > > > Signed-off-by: Jean-Philippe Brucker > A few more trivial points. I'll fix those, thanks Jean