From: Catalin Marinas <catalin.marinas@arm.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org,
Richard Earnshaw <Richard.Earnshaw@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
Andrey Konovalov <andreyknvl@google.com>,
Kevin Brodsky <kevin.brodsky@arm.com>,
Peter Collingbourne <pcc@google.com>,
linux-mm@kvack.org, Vincenzo Frascino <vincenzo.frascino@arm.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH v2 19/19] arm64: mte: Add Memory Tagging Extension documentation
Date: Thu, 12 Mar 2020 09:50:22 +0000 [thread overview]
Message-ID: <20200312095022.GA5801@mbp> (raw)
In-Reply-To: <0857cca0-9f75-398d-e755-f645d2d8a594@linaro.org>
On Wed, Mar 11, 2020 at 03:17:54PM -0700, Richard Henderson wrote:
> On 2/26/20 10:05 AM, Catalin Marinas wrote:
> > + /*
> > + * From include/uapi/linux/prctl.h
> > + */
> > + #define PR_SET_TAGGED_ADDR_CTRL 55
> > + #define PR_GET_TAGGED_ADDR_CTRL 56
> > + # define PR_TAGGED_ADDR_ENABLE (1UL << 0)
> > + # define PR_MTE_TCF_SHIFT 1
> > + # define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
> > + # define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
> > + # define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
> > + # define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
> > + # define PR_MTE_TAG_SHIFT 3
> > + # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
>
> Is there a reason not to include TCMA into the set of bits that userland can
> control with this prcrl?
>
> I know that ordinarily TCR_ELx requires expensive syncing, but for this
> particular field there is a note about "software may change this control bit on
> a context switch". Which I take to mean that the usual TLB-related syncing may
> be omitted.
TCMA (unlike TCF) is allowed to be cached in the TLB. If we are to allow
the user to configure this field, there are two approaches, each with
its own problems:
1. per-thread TCMA (as we do with TCF). Since the field is cached in the
TLB (ASID-tagged), we'd have to invalidate the TLB for that ASID
every time we switch between threads of the same process on a CPU.
2. per-process TCMA. This solves the problem of TLB invalidation,
however you'd have to synchronise all the threads that may run on
other CPUs. A simple IPI (as in sys_membarrier() for example) is not
sufficient since with CnP (CPU threads sharing the TLB) we'd need a
synchronous update. This leaves us with a stop_machine() call and I'm
not keen on exposing this to user via a syscall.
If you have a strong need for TCMA in user space, please raise it and we
can discuss about always allowing match-all tags for user tasks. Note
that the kernel will have match-all enabled for kernel addresses.
--
Catalin
prev parent reply other threads:[~2020-03-12 9:50 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-26 18:05 [PATCH v2 00/19] arm64: Memory Tagging Extension user-space support Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 01/19] arm64: alternative: Allow alternative_insn to always issue the first instruction Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 02/19] arm64: mte: system register definitions Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 03/19] arm64: mte: CPU feature detection and initial sysreg configuration Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 04/19] arm64: mte: Use Normal Tagged attributes for the linear map Catalin Marinas
2020-03-05 16:21 ` Steven Price
2020-03-05 16:38 ` Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 05/19] arm64: mte: Assembler macros and default architecture for .S files Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 06/19] arm64: mte: Tags-aware clear_page() implementation Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 07/19] arm64: mte: Tags-aware copy_page() implementation Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 08/19] arm64: Tags-aware memcmp_pages() implementation Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 09/19] arm64: mte: Add specific SIGSEGV codes Catalin Marinas
2020-02-26 19:05 ` Eric W. Biederman
2020-02-26 19:26 ` Catalin Marinas
2020-02-26 22:33 ` kbuild test robot
2020-02-27 11:05 ` Catalin Marinas
2020-02-27 15:20 ` Eric W. Biederman
2020-02-26 18:05 ` [PATCH v2 10/19] arm64: mte: Handle synchronous and asynchronous tag check faults Catalin Marinas
2020-02-27 11:50 ` Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 11/19] mm: Introduce arch_calc_vm_flag_bits() Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 12/19] arm64: mte: Add PROT_MTE support to mmap() and mprotect() Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 13/19] mm: Introduce arch_validate_flags() Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 14/19] arm64: mte: Validate the PROT_MTE request via arch_validate_flags() Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 15/19] mm: Allow arm64 mmap(PROT_MTE) on RAM-based files Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 16/19] arm64: mte: Allow user control of the tag check mode via prctl() Catalin Marinas
2020-03-09 13:53 ` Kevin Brodsky
2020-02-26 18:05 ` [PATCH v2 17/19] arm64: mte: Allow user control of the generated random tags " Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 18/19] arm64: mte: Kconfig entry Catalin Marinas
2020-02-26 18:05 ` [PATCH v2 19/19] arm64: mte: Add Memory Tagging Extension documentation Catalin Marinas
2020-03-09 14:30 ` Kevin Brodsky
2020-03-11 22:17 ` Richard Henderson
2020-03-12 9:50 ` Catalin Marinas [this message]
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