From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <will@kernel.org>, <mark.rutland@arm.com>,
<catalin.marinas@arm.com>, <aneesh.kumar@linux.ibm.com>,
<akpm@linux-foundation.org>, <npiggin@gmail.com>,
<peterz@infradead.org>, <arnd@arndb.de>, <rostedt@goodmis.org>,
<maz@kernel.org>, <suzuki.poulose@arm.com>, <tglx@linutronix.de>,
<yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>
Cc: <yezhenyu2@huawei.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>
Subject: [RFC PATCH v4 2/6] arm64: Add level-hinted TLB invalidation helper
Date: Tue, 24 Mar 2020 21:45:30 +0800 [thread overview]
Message-ID: <20200324134534.1570-3-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200324134534.1570-1-yezhenyu2@huawei.com>
From: Marc Zyngier <maz@kernel.org>
Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index bc3949064725..a3f70778a325 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -10,6 +10,7 @@
#ifndef __ASSEMBLY__
+#include <linux/bitfield.h>
#include <linux/mm_types.h>
#include <linux/sched.h>
#include <asm/cputype.h>
@@ -59,6 +60,35 @@
__ta; \
})
+#define TLBI_TTL_MASK GENMASK_ULL(47, 44)
+
+#define __tlbi_level(op, addr, level) \
+ do { \
+ u64 arg = addr; \
+ \
+ if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \
+ level) { \
+ u64 ttl = level; \
+ \
+ switch (PAGE_SIZE) { \
+ case SZ_4K: \
+ ttl |= 1 << 2; \
+ break; \
+ case SZ_16K: \
+ ttl |= 2 << 2; \
+ break; \
+ case SZ_64K: \
+ ttl |= 3 << 2; \
+ break; \
+ } \
+ \
+ arg &= ~TLBI_TTL_MASK; \
+ arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
+ } \
+ \
+ __tlbi(op, arg); \
+ } while(0)
+
/*
* TLB Invalidation
* ================
--
2.19.1
next prev parent reply other threads:[~2020-03-24 13:46 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 13:45 [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-03-24 13:45 ` Zhenyu Ye [this message]
2020-03-24 13:45 ` [RFC PATCH v4 3/6] arm64: Add level-hinted TLB invalidation helper to tlbi_user Zhenyu Ye
2020-03-24 14:19 ` Marc Zyngier
2020-03-25 2:47 ` Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 4/6] mm: Add page table level flags to vm_flags Zhenyu Ye
2020-03-24 18:44 ` Steven Rostedt
2020-03-25 2:10 ` yezhenyu (A)
2020-03-24 13:45 ` [RFC PATCH v4 5/6] arm64: tlb: Use translation level hint in vm_flags Zhenyu Ye
2020-03-24 14:45 ` Marc Zyngier
2020-03-25 8:00 ` Zhenyu Ye
2020-03-25 14:13 ` Marc Zyngier
2020-03-26 7:11 ` Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 6/6] mm: Set VM_LEVEL flags in some tlb_flush functions Zhenyu Ye
2020-03-24 15:01 ` [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature Peter Zijlstra
2020-03-25 4:49 ` Zhenyu Ye
2020-03-25 13:32 ` Peter Zijlstra
2020-03-26 7:15 ` Zhenyu Ye
2020-03-25 16:15 ` James Morse
2020-03-25 16:41 ` Peter Zijlstra
2020-03-26 6:45 ` Zhenyu Ye
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