From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FFF7C2BA19 for ; Thu, 23 Apr 2020 10:38:55 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 32F9120787 for ; Thu, 23 Apr 2020 10:38:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 32F9120787 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id F37038E0005; Thu, 23 Apr 2020 06:38:53 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id EE7C88E0003; Thu, 23 Apr 2020 06:38:53 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id DFDFC8E0005; Thu, 23 Apr 2020 06:38:53 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0028.hostedemail.com [216.40.44.28]) by kanga.kvack.org (Postfix) with ESMTP id C59578E0003 for ; Thu, 23 Apr 2020 06:38:53 -0400 (EDT) Received: from smtpin18.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay03.hostedemail.com (Postfix) with ESMTP id 7F769824805A for ; Thu, 23 Apr 2020 10:38:53 +0000 (UTC) X-FDA: 76738771746.18.jelly47_307b0499e6808 X-HE-Tag: jelly47_307b0499e6808 X-Filterd-Recvd-Size: 2819 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by imf29.hostedemail.com (Postfix) with ESMTP for ; Thu, 23 Apr 2020 10:38:53 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1520531B; Thu, 23 Apr 2020 03:38:52 -0700 (PDT) Received: from gaia (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A54943F68F; Thu, 23 Apr 2020 03:38:50 -0700 (PDT) Date: Thu, 23 Apr 2020 11:38:48 +0100 From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon , Vincenzo Frascino , Szabolcs Nagy , Richard Earnshaw , Kevin Brodsky , Andrey Konovalov , Peter Collingbourne , linux-mm@kvack.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v3 10/23] arm64: mte: Handle synchronous and asynchronous tag check faults Message-ID: <20200423103847.GC4963@gaia> References: <20200421142603.3894-1-catalin.marinas@arm.com> <20200421142603.3894-11-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200421142603.3894-11-catalin.marinas@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Tue, Apr 21, 2020 at 03:25:50PM +0100, Catalin Marinas wrote: > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index ddcde093c433..3650a0a77ed0 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -145,6 +145,31 @@ alternative_cb_end > #endif > .endm > > + /* Check for MTE asynchronous tag check faults */ > + .macro check_mte_async_tcf, flgs, tmp > +#ifdef CONFIG_ARM64_MTE > +alternative_if_not ARM64_MTE > + b 1f > +alternative_else_nop_endif > + mrs_s \tmp, SYS_TFSRE0_EL1 > + tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f > + /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ > + orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT > + str \flgs, [tsk, #TSK_TI_FLAGS] > + msr_s SYS_TFSRE0_EL1, xzr > +1: > +#endif > + .endm > + > + /* Clear the MTE asynchronous tag check faults */ > + .macro clear_mte_async_tcf > +#ifdef CONFIG_ARM64_MTE > +alternative_if ARM64_MTE > + msr_s SYS_TFSRE0_EL1, xzr > +alternative_else_nop_endif This needs a 'dsb ish' prior to the msr as an indirect write (async tag check fault) to the TFSRE0_EL1 register is not ordered with a subsequent direct write (msr) to this register. The check_mte_async_tcf macro is fine as we execute it after taking an exception with SCTLR_EL1.ITFSB bit set (which triggers such synchronisation). -- Catalin